IBM 0.13um CMOS layout question.

cmrf8sf

Hi, has anyone used cmrf8sf tech before?

I am stucked with nfet transistor (nfet_inh and nfet_rf are okay). How can I connect the B-terminal to ground in layout? Do I use nTiedown?

I have tried subc, nTiedown, not working.

Any suggestions? Thanks!

contact substrat ibm 0.13

Hi, everyone

Did I make myself clear?

Could anyone help me, please?

Thanks a lot!

ibm subc

Hi,

I don't know the cmrf8sf technology but anyway for every technology you need PTAP to connect the B terminal of a NMOS.
What are "subc, nTiedown", type of contact?
When you choose your contact just make sure it's just active area, contact, m1 and of course P implant!!

Franck.

edaboard + 0.13um

Franck. thanks for that

Here is the probelm, I don't know which one is PTAP in cmrf8sf.

Subc is substrate contact and should be the one, but unfortunately, it dosen't work.

Cheers
Jerry

ibm 0.13

Sub cont for Nmos

PIMP - active(or pdiff or diff) - M1 - Cont

Sub Cont for Pmos

NIMP - active(or ndiff or diff) - M1 - Cont

Read your Layer Usage or Device Formation doc and accordingly use the layers.

ayout 0.13 um

Thanks1
But there is no PIMP or NIMP in the library.

I have used nTiedown (active, cont, M1) and pTiedown, they didn't work.

Jerry

0.13um cmos

Hi,

1) I suppose you have LVS problem with your nfet. Could you explain what is this problem?
2) Is this mos come with a deep nwell or anything like that (I mean in the layout)?
3) Did you try to LVS this nfet only in a test case cell?
4) Did you try to create a "flat tie" just by drawing active, some contact and connect it to the right net?
If you don't have any implant layer in this kit it means you just have to draw active in the substrate to create a PTAP ... or there is a trick ... which should be written somewhere in the doc.
5) Try to do the same as in the working fets: nfet_inh and nfet_rf. In the layout you should have ptap somewhere if it's working. By the way is nfet_inh means inhereted substrate connection?
6) Are you sure you connected the B terminal of the nfet in your schematic?

Franck.

ibm cmos 13 course

HI, Franck

1) It is a LVS problem with my nfet. It says the B-terminal should connect to GND which I think I have.

2) No, there is no nwell for this.

3) Yes, I try to LVS this nfet only in a test case cell. It's a simple inverter.

4) Yes, I tried this method too, didn't work. Unfortunately, the document is a little poor. Not much information about the substrate.

5) nfet_inh means inhereted substrate connection. For nfet _rf, I don't have to add anu substrate connection, it's already built in. For nfet_inh, I used nwell contact to connect pfet and nTiedown for nfet. They all work properly.

6) I am sure that I have connected the B terminal of the nfet in the schematic.

Thanks
Jerry

Re: ibm cmos 13 course

HI,jerrymelb.
have u over come with the ibm cmos 13 sub's problem? if u did it, could you tell me how to do it. thank very much

Hi jerrymelb,

I would suggest as franck said a simple test case with one nfet only with it's pins around every terminal and a subc component from body terminal to VSS.Then run LVS for this test case?Does it pass or not?

I used this technology a couple of years ago and i don't remember such an issue for the regular transistors (nfet,pfet).What i did for nfet was to to connect the respective terminal (drain or source according to the schematic connection) to VSS line in the layout and then this line was connected to the substrate ring (ring of subc contacts) with M1 metal...My LVS was clean...

The tie-down devices you mentioned are reverse biased diodes and are not used to connect the respective schematic terminal of the transistor to VSS in the layout...they are used because some devices require a current path to prevent charge build-up and damage during wafer processing.This current path is typically provided by a reverse-biased diode called a "tie-down" diode.These are typically n+/substrate or p+/n-well diodes.You should connect those diodes to the gate of all transistors (with M1 metal before changing to other metal layer) and other points in the layout according to the floating-gate check that you will establish at the end of your design and before tape out.

Regards,
Jimito13

Hi jimito13,
for the first question, I will show you my simple 'nfet' design. Just as you have seen, I have got subc around my nfet, and get the subc connected with the 'GND' on the M1 metal layer, but I cannot pass the LVS test. By the way , I use IBM .13um. Calibre.
the second question, I understand the means of using the tie-down devices, but at practice, there are little useful information mentioned in the design kit help. I confused with the diodes mentioned in the library, which should I choose,(for example, diffhavar ,dipdnw ,dvpnp,havar,sbd), and how connected with it.
thanks for your replay!

Best Regards,
Sue

Re: ibm cmos 13 course

P.S: I'm a new designer. I didn't understand the VSS line you mentioned in the replay, do you mean the terminals(drain and source) should connected just as the schematic, and the body terminal should connect with the subc with the VSS line?

Hi lamar_sue,

At first,i must say that i have never used calibre for a long time so i am not an expert with it's error reports.I would suggest that you used Assura for LVS if you expect help from me!The pictures in the pdf file seem to be ok,i didn't see something wrong.

I didn't understand the VSS line you mentioned in the replay, do you mean the terminals(drain and source) should connected just as the schematic, and the body terminal should connect with the subc with the VSS line?

Click to expand...

What i do for GND/VSS is to connect all sources of the nmos transistor (S from all fingers for your test case) with another (higher than M1) metal together (and add the respective viases of course) on a line of a higher metal in the stack and then this line is directly connected with M1 to subc ring.But for this simple case as yours everything looks fine from your side.Give it a try with assura and if the problem persists then report it to your supervisor/professor and he will send a mail to MOSIS (or any other pdk representantive) for more effective support and a final solution.

Regards,
Jimito13

To be clear, pls show your nFET cross section with picture. Others can't help before getting know where's B-.

Hi, leo_o2
I just show you the pictures which I make some notes on this，but the cross section? Sorry, I didn't understand very well, which part do you refer to............

Thanks for your reply.

Thanks for your reply. Recently my lab's assura didnot work very well, because there are some mistakes in it. So we just can only rely on Calibre. Maybe I think it depends on IBM .13um or Calibre, not my faulty.


Regards,
Lamar_sue

Ok,let's give it another try...Remove the subc component from your schematic and then pull a wire from body(B) terminal of your nfet with name sub! (which is global).Then remove the subc ring from layout and the subc pin if it exists.Update conponents and nets and then remove from layout whatever concerns subc/sub! namings (maybe there will exist a pin sub! that's why i say that).LVS again now and let me know the result.

thanks. I have already solve this error. It all because model library, the latest version does not work very well, so I come back to the earilier version, and all are correct. Nevertheless, thank you very much!

Ok.It is weird that an earlier version has the problem and the latest not...But in any case,you should report that to IBM to be solved.

Regards,
Jimito13