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Power Estimation for an Implimantation?

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Mirzaaur

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Dear all,

Is it possible to estimate the power of our vhdl implimented design. apart from system parameters it depends on technology. Is there any tool which can estimate for power on a required clock and technology for ASIC for ceratin no. of operations?

thaks for your time,
attiq
 

Yes, synopsys and cadence both provide the tools for power estimation.
But the accuracy may be a problem.
 

you can use power theater or power compiler
 

Hi Mirzaaur,

You'd better estimate the power at gate level. And you should alos privide a SAIF(from simulation toll based on your pattern) like file to let the tool know the toggle possibility of the netlist.
 
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