to generate a digital signal

`timescale 1ns/1ps
module phase_comp(
   // Outputs
   x_out, 
   // Inputs
   clk1, clk2
   );
   input clk1, clk2;
   output      x_out;
   reg         clk2_r, clk2_rr;

   assign      x_out = clk2_rr;
   always @(posedge clk1) begin
      clk2_r <= clk2;
      clk2_rr <= clk2_r;
   end
endmodule // phase_comp

module test();
   reg                  clk1;
   reg                  clk2;
   wire                 x_out;

   phase_comp phase_comp(
                         // Outputs
                         .x_out         (x_out),
                         // Inputs
                         .clk1          (clk1),
                         .clk2          (clk2));
   reg         clk;
   reg [1:0]   count;
   reg         sel;
   
   always @(count or sel) begin
      clk1 <= sel ? count[0] : count[1];
      clk2 <= sel ? count[1] : count[0];
   end
     
   initial begin
      $shm_open("WAVEFORM");
      $shm_probe(test, "AS");
      count = 0;
      sel = 0;
      clk = 0;
      #400;
      sel = 1;
      #400;
      $finish;
   end // initial begin
   always @(posedge clk) begin
     count[0] <= count[1];
     count[1] <= ~count[0]; 
   end

   always #5 clk = ~clk;
endmodule // test