how coulud i know that the dual port ram have been built ?

how coulud i know that the dual port ram have been built successfully?
the following step(quartus 5.0):
1。first tool->megawizard plug-in manager,then select "memory compiler",then select " ram-2-port"，option is：
one read only port,one write only port;
the data width of the read port is 16 bit,and the data width of the address port is 12 bit;two port share one clock .
the data width of the read port is 8 bit,and the data width of the address port is 13 bit;
2。build a file named ram2port.vhd
3。the following is the code ：
LIBRARY IEEE;
USE IEEE.Std_Logic_1164.ALL;
USE IEEE.Std_Logic_Unsigned.ALL;
USE IEEE.Std_Logic_Arith.ALL;

ENTITY ADSAMPLE IS
PORT
(
SysClk : in Std_Logic;
Led : out std_logic_vector(3 downto 0);
Rst : in std_logic;
);
END ADSAMPLE;

ARCHITECTURE Action OF ADSAMPLE IS

component ram2port IS
PORT
(
data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
wren : IN STD_LOGIC := '1';
wraddress : IN STD_LOGIC_VECTOR (11 DOWNTO 0);
rdaddress : IN STD_LOGIC_VECTOR (12 DOWNTO 0);
clock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
);
......
--bulid an array named rambit_1[2048],an element 16 bit，
subtype ramWord_1 is std_logic_vector(15 downto 0);
type ramWordType_1 is array (0 to 11) of ramWord_1;
signal ram16bit_1 :ramWordType_1;
--build an array named rambit_1[4096],an element 8 bit，

subtype ramByte_1 is std_logic_vector(7 downto 0);
type ramByteType_1 is array (0 to 12) of ramByte_1;
signal ram8bit_1 :ramByteType_1;

u6:ram2port port map
(
data => ram16bit_1(dualPortRamWrAddrCount_1),
wren =>'1',
wraddress => conv_std_logic_vector(dualPortRamWrAddrCount_1,12),
rdaddress => conv_std_logic_vector(dualPortRamRdAddrCount_1,13),
clock => SysClk,
q => ram8bit_1(dualPortRamRdAddrCount_1)
);
END component;

the compile result is ：
Total memory bits 0/230616 ?
why?

Re: how coulud i know that the dual port ram have been built

Hi lzh08,

You can use this ram model's simulation model, do some simulation, and check the waveform to make sure it's okay!