Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

how to improve timing?

Status
Not open for further replies.

arbalez

Member level 5
Member level 5
Joined
Jan 22, 2005
Messages
82
Helped
3
Reputation
6
Reaction score
1
Trophy points
1,288
Activity points
734
is the timing performance merely depends on the code written? how to improve the timing performance?

everytime i synthesize my code, the timing requirement is usually not met. i'm using quartusII.
 

The timing is mainly depended on the code.
But you can improve your timing by set your FPGA's speed grade,
And set some constraints on I/O of your code .
 

    arbalez

    Points: 2
    Helpful Answer Positive Rating
Some techniques to increase speed: Use pipelining, short carry chains, short routes, and low fanout.
 

    arbalez

    Points: 2
    Helpful Answer Positive Rating
Hi arbalez,

Yes, your code is the key. But you can also fix some small vilation by upsize cell,

rerouting, change the datapath structre.
 

    arbalez

    Points: 2
    Helpful Answer Positive Rating
how about partitioning the logics into managable blocks, does it help (improve the timing)?
 

arbalez said:
how about partitioning the logics into managable blocks, does it help (improve the timing)?
If that results in shorter routes, then probably yes. In one of my projects, the Xilinx FPGA placer wanted to arrange my large multi-stage design as one big bowl of spaghetti. The result was numerous long routes and hopeless timing. So, I applied location constraints to my stages, and then the tools had no problem meeting my timing, and finished much sooner.
 

    arbalez

    Points: 2
    Helpful Answer Positive Rating
Alos all of the FPGA makers has app notes it calll HDL coding styles, Xilinx xas section in there ISE documentation, it is around 100 pages look there as well
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top