problem in understanding "Timing report" gerated b

hi,

When you synthesis your design using cadance buildgates, generates a timming report.
In the report, could some please explain me the meaning of some terms like .

Other End Arrival Time 0.00
- External Delay 1.50
+ Phase Shift 10.00
= Required Time 8.50
- Arrival Time 1.31
= Slack Time 7.19

This is the timming report i got .

In this what do yo means by "REQUIRED TIME", "ARRIVAL TIME", "EXT DELAY","PHASE SHIFT".

I calculate the total time delay by T = PHASE SHIFT - SLACK TIME
and maximun frquency by F = 1 / T.

Pls help me if i am wrong .

Thanks for you help in advance

dinesh P

Re: problem in understanding "Timing report" gerat

The timing report that Build Gates gives will have more information regarding the delays in the circuit and the path with the longest delay. The key points to be noted from this report are:

"REQUIRED TIME", "ARRIVAL TIME", "SLACK", "CRITICAL PATH".

REQUIRED TIME : This is the time that you have specified in the constraints file for the signals. You may have specified a Clock Freqency when synthesizing the design. This clock frequency is broken down into a set of time constraints and defines the setup and hold times.

ARRIVAL TIME: This is the time taken for the signals to arrive at that point. This is determined by the synthesis tool using the technology library files. This denotes the actual delays or time the signal arrives at that point.

SLACK: This is the difference between the REQUIRED TIME and the ARRIVAL TIME. SLACK should be zero or positive. Positive slack indicates that the data arrives earlier than expected and that there is enough time for the signal. This means that the SETUP and HOLD times are not violated.

NEGATIVE slack means that the data is arriving later than the time specified by you. This will lead to SETUP and HOLD time violations. Positive slack is good whereas Negative slack should be avoided.

CRITICAL PATH: This is the path with the longest delay in the design. This path determines the maximum operating frequency. For example, if the report states that Path i has the longest delay of tns and is the critical path, then the maximum operating frequency of the design is 1/tHz.

Am not too sure about the phase shift term.. I'll have to check that out and let you know.