magnetra
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Which one should I learn, VHDL or Verilog?
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emadi said:verilog is more advanced from vhdl
Verilog widely used in the industry, it is very powerful language for verification,
it is easy to learn..if you know C prog...
Where as VHDL very decriptive language ...but very powerful for synthesis of circuits...
One FPGA & ASIC designs in Verilog => very easy for writting & friendly syntaxes like C.
One FPGA design in VHDL ==> Very easy to imagine the Hardware components while writting RTL & simulation.