davyzhu
Advanced Member level 1
![Advanced Member level 1](/styles/images/ranks/glevel1.gif)
Hi all,
I was asked in interview, but I am not familiar with DC
"While synthesis of a design using synopsys design compiler, why do you specify input and output delays?"
Is these delay related to Tsu, Thd, and Tcq?
Any suggestions will be appreciated!
Best regards,
Davy
I was asked in interview, but I am not familiar with DC
"While synthesis of a design using synopsys design compiler, why do you specify input and output delays?"
Is these delay related to Tsu, Thd, and Tcq?
Any suggestions will be appreciated!
Best regards,
Davy