zhi_yi
Full Member level 4
hi there, please help me, i got a little confused with this circuit, please give a correction, is it from the circuit would be like this? if the load increases, then the current flow through the load would be decreased because of the capacitor would be discharging its charge slowly (Vc = Vload = Vin.e^-t/RC), and the voltage through the load would just fall a little, so the difference between Vref and the output divider would just fall a little too, so the output from the error amplifier would not be so high, so, the headroom voltage would be lower, its mean that the resistance in collector emitter is low, and will providing more current through the load, and if the load is decreased, for example we short the two terminal of the capacitor, then, the load current would be exceeded, and the output voltage will fall, so, the voltage in the divider output that connect to the inverting will drop too, so, the difference between the Vref and the Voltage divider would be high, and the output from the error amplifier will be high too because Vout = A(V+ - V-), and it would makes the Collector emitter voltage rise, and its mean that the resistance in the collector emitter would be rise too, and limit the exceeded current to flow to the load, is it true? please correct me...
thank you very much
thank you very much