Design a 1-bit fulladder using a decoder and 2 "or&quot

Hi all,

There is another interview problem:

Design a 1-bit fulladder using a decoder and 2 "or" gates?

Any suggestions will be appreciated!
Best regards,
Davy

Re: Design a 1-bit fulladder using a decoder and 2 "or&

Hello,
I think this may help.

A, B are your addends
C = Carry Input
S = Sum Output
Y = Carry Out

1.) The Truth Table Looks like this:
A B C : S Y
0 0 0 : 0 0
0 0 1 : 1 0
0 1 0 : 1 0
0 1 1 : 0 1
1 0 0 : 1 0
1 0 1 : 0 1
1 1 0 : 0 1
1 1 1 : 1 1


2.) Connect your Inputs (ABC) to 3 -to -8 DECODER inputs in that order ABC.

3.) I am not sure if there is a positive logic output decoder. I used once the 74LS138 3 -to -8 decoder but it is a negative logic output. If you can find a positive logic out put 3 - to - 8 decoder then it is possible to implement your problem. but otherwise you need inverters.

4.) You didn't say how many inputs are there in your OR gate so I assume that this its input is variable.

5.) Basically connect the outputs of the decoder to the inputs of the 4 - input OR gate using the following equation.

S (Sum) = Σm(1,2,4,7)
Y (Carry Out) = Σ (3,5,6,7)

Hope this help