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As far as I know specific cells in FPGA design should be replaced with ASIC vendors' ones. You should replace build-in memory blocks as well. But, more comments are welcome...
Are there any literature about this issue? Perhaps some whitepapers from companies dealing with this issue?
1. You must get a synthesis library from which the fab you want to foundry.
2. Synthesis yor logic design ( HDL coding) to gate level netlist
3. APR your design
FPGA's have many resources inbuilt such as memories, multipliers, busses even microprocessor, so while going for an ASIC for the same design we need to consider the above and use an appropriate library which contains a few of the above features(multiliers, ADC, DAC etc).
please do refer this, may get some extra feature ideas **broken link removed**
there are more differences in implementing an IC in FPGA and in ASIC.
using FPGA, we can use the available resources or blocks in it. but for ASIC implementation we need to add all the blocks like multipliers,memories,PLLs etc.
implementation in ASIC, can be for large chips & high freequency chips.
but if the area is large, we need to split the logic into multiple FPGAs, so operating freequency may reduce.
after imlemnting in PFGA for validation, we will go to ASIC implementation.
for that, we need to change target libraries to ASIC vendor libs. & need to resynthesize with that lib, then P&R, then tapeout.
First imlemnting in PFGA for validation,then imlemnting ASIC .
in ASIC you need target libraries to ASIC vendor libs.
first synthesize with the lib, then P&R, then tapeout.
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