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Spartan 3 - External SRAM interface

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cmos babe

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Hi,
I want to make a FPGA-SRAM interface.This is the first time I connect the FPGA to the outside world so I need some help .
Should the clock frequency be changed to accommodate the offset in/out before/after clock time + the read/write cycle time?

Thanks (=
 

What type SRAM? What is your clock rate now?
Are you using a common FPGA board? Someone may already have example code.
 

    C

    cmos babe

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are you sure it is SRAM not SDRAM?
 

SRAM is asynchronous, so the clock is irrelevant... as long as you meet the access time of the SRAM, you will be ok. If you have a 10nS access time, that's a 100 MHz maximum clock rate you can have.... but the SRAM doesn't actually use the clock.
 

In addition to the access time there's delay introduced by the clock-to-pad path and the pad-to-setup path..Shouldn't this be added to the access time to calcaculate the max clock rate?
 

Yes you need to consider the FPGA I/O delays too. To minimize those delays, try to put your I/O registers into the IOBs instead of the regular logic fabric. Also set output SLEW to FAST. If the total delay is still too much, you can either reduce the clock frequency or add another clock cycle to your SRAM access timing.

Some of the Xilinx example projects use the SRAM:
**broken link removed**
 

    C

    cmos babe

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