pseudockb
Member level 5
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holding capacitor sample and hold
Hi, I am designing a SC sample and hold circuit as shown in the following picture. When I used a large holding cap of 1pF, the output of the opamp takes a longer time to settle down at phase 1. Furthermore, the output during phase 2 seems to deviate more from the ideal sampled value. Could someone please explain to me? I have attached the simulation result for holding cap of 100f and 1pF. Thanks
Hi, I am designing a SC sample and hold circuit as shown in the following picture. When I used a large holding cap of 1pF, the output of the opamp takes a longer time to settle down at phase 1. Furthermore, the output during phase 2 seems to deviate more from the ideal sampled value. Could someone please explain to me? I have attached the simulation result for holding cap of 100f and 1pF. Thanks