Alles Gute
Full Member level 2
delay lock loop modeling
I have been trying to model a dll in simulink but to no results.
My problem is modeling the voltage controlled delay line. I tried to use variable transport delay. But it didn't work well.
Can anybody give me an example of modeling DLL or some materials related to that?
Regards,
Alles Gute
I have been trying to model a dll in simulink but to no results.
My problem is modeling the voltage controlled delay line. I tried to use variable transport delay. But it didn't work well.
Can anybody give me an example of modeling DLL or some materials related to that?
Regards,
Alles Gute