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Disable timing check in NC-Verilog

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ywguo

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no_notifier

Hello,

I need to disable timing check for several instances on running post-layout simulation. The simulator is NC-Verilog.

Does anybody know how to disable timing check (setup time and hold time) for only several instances in NC-Verilog?


Thanks
Yawei
 

no timing check

Hi,
Perhaps you know this already: ncelab has a -notimingcheck - but that is a global switch - truns off for ALL instances.

If your concern is X-propagation due to timing violation (and not the violation iself), try using no_notifier flag, again global.

For instance specific stuff few ideas:

1. If you like this no_notifier kind of thing, it is fairly easy to create a TCL script to force notifier reg of each FF instance (that you are interested) to 0.
2. There is a PLI to do precisey what you wanted, see:
https://www.project-veripage.com/notc.php

3. IIRC, NC supports a system task named $disable_warning - to supress warnings from individual instances, search in their manual.

HTH
Ajeetha
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www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html
 

ncverilog disable_warning

Hello aji_vlsi. If we disable the timing checks , is it going to make the post simulation less accurate ? Some eda simulation tools , rounded off negative timing checks for certain fab. Is it allowable , lets say for .35um ? Does it affect the accuracy of the timing info ?

How do we confirm or say , okay it can be neglect ? If STA tools like PT check alright but post simulation have message saying that no negative timing checks done. And the value os rounded to zero ? So is it valid , the post simulation if functional checks alright .

Thx in advance.
 

ncverilog no_notifier

Hi,

wls said:
Hello aji_vlsi. If we disable the timing checks , is it going to make the post simulation less accurate ?
Click to expand...

Yes indeed, but that's where user intervens and says: i know this interface well, in real life these sginals don't toggle this way, hence let me ignore/turn them off.

Some eda simulation tools , rounded off negative timing checks for certain fab. Is it allowable , lets say for .35um ? Does it affect the accuracy of the timing info ?
Click to expand...

Many simulators do provide a way to enable -ve timing checks (-neg_thck ?)

I would prefer not to ignore -ve delays - unless you know what and why you are doing that.

How do we confirm or say , okay it can be neglect ? If STA tools like PT check alright
Click to expand...

Rely more on STA, do DTA (Dynamic, simulation) only for asynchronous stuff, sanity check and some functional tests.
but post simulation have message saying that no negative timing checks done. And the value os rounded to zero ? So is it valid , the post simulation if functional checks alright .

Thx in advance.
Click to expand...

As I mentioned, there are tool options to make these warnings disappear.

HTH
Ajeetha
--
www.noveldv.com
Interested in expert PSL/SVA training in Bangalore?
Visit www.noveldv.com/cvc.html
 

negative timing check

Hi, Ajeetha,

Thanks very much. I really need to prevent the X state propagation.

I try the option -nonotifier for ncelab. Now it doesn't shown any timing violation and X state at the waveform.


Yawei
 

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Re: negative timing check

I would be suggest you to edit the SDF file for the particular instance make it ZERO. This will make your task easy.... (Make a copy of original SDF for future use).

-paulki
 

    V

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Re: negative timing check

Is there a way to disable $width timing check on the FF's ck input?
We have logic designed where the ck can be short pulses, and the FF output corrupts because $width timing is violated, although the d input doesn't change.
We want to prevent X propagation in this case.

We use ius v92 and looks like there's not a way to only disable $width timing checks.
Does the latest ius version support disabling different types of timing check separatelly?
 
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