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If a chip is pad limited, you've got more I/Os than can be fit on the die.
One solution might be to see if there are I/Os you can get rid of. If possible, in parallel, try and understand the cost difference if you went to a larger die and maybe a larger package if you needed to keep all I/O. Having unused space in core might be a good thing - it might allow you to operate at faster frequencies or add more functionality in the future.
If a chip is core limited, too much logic and can't fit in the die. Can any logic be removed? If not, then see what it would take to bring it to a larger die and/or a larger package.
By pad continuity, I think you mean keeping the same pad assignments on the die. You might need to change them if you go with a bigger die.
If the chip is pad limited, you can do the following:
1. See if you can reduce the width of any data busses. One way to do this is to half the size of the bus and double its speed, so that the bandwidth is maintained.
2. See if some of the pins can be shared. These pins will have dual functionality, which can be configured by the chip.
3. See if flip-chip packaging is feasible, that way you can put mulitple rows of pads on each side.
4. Add your name and photo on the white spaces in the chip
If the chip is core limited, you can do the following:
1. Remove any redundant/unused logic
2. Consider removing some functions that are not important
3. Move to a smaller technology
Of course, if you don't care about die size, you can simply grow the chip size without worrying about any of the above.
Pad limit pad is long and narrow. Core limited pad is fat and shorter. This make sense as overall area is smaller.
Most pad libraries for 0.1*um are pad limited. I have not seen a core limit pad for deep sub micron.
There is only additional requirement for core-limited pad. The huge PMOS and NMOS for ESD protection are put on both end of the pad (ie. [PMOS Logic NMOS]), alternate pads are always flipped so that PMOS faces a PMOS and NMOS faces a NMOS. It is good to reduce PMOS-NMOS junctions for huge transistor. (pad limit pad have the pmos and nmos stack on top of one another, so no need to flip).
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