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How should I define a clock at the output of MUX?

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vahid_roostaie

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Hi!

I have Muxed clocks in my design.there is no relationship between these two clocks
I used create_clock to define the two clocks and I want to know that:

how should I define the clock at the output of the MUX should I use create_clock for this pin or create_generated_clock?

what about MUX select signal?

please help me to solve this problem that how can I synthesis and analyze this clock Muxing in DC_shell?

thanks for your help
 

muxed clock

hi,

use create_generated_clock
and set_case_analysis "1 or 0" [get_ports "your mux sel input"]
 
muxed clock not working

I have used set_case_analysis with "get_pins" because the mux select signal is generated internaly is this way ok?but when I want to specify the mux select signal input DC can't find that I found the mux select signal from the verilog netlist file after analyze and elaborate is this ok?

this is the command I used and DC rejected it :

set_case analysis 0 [get_pins digital_core/controller/B_6/Z_0]

Z is the output port of a buffer that mux select signal is connected to it's input in the netlist.
 

clock mux

Give me DC error message

and try with mux select input ... [get_pins mux_path/sel]
 

muxing clock

hi vahid,

Ur sel_input is internally generated and DC cant find the pin.

I assume u did a top to bottom synthesis and ur clock_mux is one module.

2 modules:
1) top_mod
2) clock_mux

Therefore, ur current_design is top_mod. To assign set_case_analysis on the sel_pin, u must make clock_mux module as a current module and then set_case_analysis to sel_pin.

Hope this helps
-no_mad
 

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