Lantis
Junior Member level 3
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I have designed a 6bit Pipelined ADC. However, I got some problem when i design the reference voltage circuit.
Because I have no output pad for VREFP(1.75V) and VREFN (1.25V) , so I add a large cap (about 400pF) on chip. I wonder which kind of OPAMP I should use.
For a one stage( folded) opamp, the large cap let the bandwidth very low ( about 1K~100KHz), the vreference voltage will be changed when the clock are switching, and the reference voltage recoverd very slowly.
So I used two stage opamp, and used a resistor seriesed with the miller capacitance so as to cancel the output pole. The BW is much larger than the folded ones.
I am not sure it will be work or failed. PLz give me some advice!! Thanks!!!
Because I have no output pad for VREFP(1.75V) and VREFN (1.25V) , so I add a large cap (about 400pF) on chip. I wonder which kind of OPAMP I should use.
For a one stage( folded) opamp, the large cap let the bandwidth very low ( about 1K~100KHz), the vreference voltage will be changed when the clock are switching, and the reference voltage recoverd very slowly.
So I used two stage opamp, and used a resistor seriesed with the miller capacitance so as to cancel the output pole. The BW is much larger than the folded ones.
I am not sure it will be work or failed. PLz give me some advice!! Thanks!!!