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Delay in design when we insert a MUX / DEMUX ??? Why ?

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yesme@

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I 've heard that it will lost a big delay when a data path have a MUX/DEMUX. I thing that it costs some delay but don't thing that it is too much.

Some case it looks like some AND, OR gates ?

Can anyone explain this problem ?
 

All gates added in any path will add delay. Whether the delay added is acceptable or not depends on the specification and requirements of your design. If the design functionality need a multiplexer then you have to have it anyway.
 

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    yesme@

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adding mux or demux or any gate will introduce some delay. its unavoidable.

if that delay results in timing violations, then constraint that path as a multicycle path.

Added after 39 seconds:


adding mux or demux or any gate will introduce some delay. its unavoidable.

if that delay results in timing violations, then constraint that path as a multicycle path.
 

Delays are not a big problem in asynchronous design. But for synchronous design, it is a severe problem. Calculate all the delays in terms of its Maximum value (Normally devices will have min, max and typical delays), and accordingly select the clock.

Best Regards.
 

Who can point to me the guidelines in the desing of a Multiplexer or a Demultiplexer? I'm quite new to this topic.. and having met it in the my chain (and having to deal with some other components...) I would like to know which are the most significative parameters characterizing this element ...

Thanks in advance for your cooperation.

Lupin
 

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