ulaska
Member level 3
i will use XC9572XL.
i draw the PLD circuit in Xilinx WebPack ISE 7.1 Project Navigator.
it doesnt gives any error. But some warnings about some lines in asynchronous .
"Possible asynchronous logic: Clock pin 'FIO3.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'."
what can i do?
Thanks.
i draw the PLD circuit in Xilinx WebPack ISE 7.1 Project Navigator.
it doesnt gives any error. But some warnings about some lines in asynchronous .
"Possible asynchronous logic: Clock pin 'FIO3.CLKF' has multiple original clock nets 'CS2_INV' 'A12' 'IOWR_INV' 'A19' 'A20' 'A21'."
what can i do?
Thanks.