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4 bit binary counter in FPGA (using VHDL)

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sanjana

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hi folks
i am beginner in vhdl coding.
i implemented a 4 bit binary counter using vhdl and downloaded the same in
FPGA . The program is not working correctly in FPGA.The count is jumping
randomly b/n any value from 0 to 15.
The coding is done in behavioural model and the the FPGA used is of xilinx.
hope someone could help me
 

counter in FPGA

Show us your code. Please use the "code" button so your source code appears properly indented.
 

Re: counter in FPGA

The code is pretty simple:

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(txclk,grst:in std_logic;
     cnt_out:out std_logic_vector(7 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(7 downto 0);
begin
count:process(grst,txclk)
begin
  if grst='1' then
	cnt<="00000000";	 
  elsif rising_edge(txclk) then
        cnt <=cnt + "00000001";
  end if;
end process;
cnt_out<=cnt;
end counter;
[/code]

Added after 2 minutes:

The code is pretty simple :

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(txclk,grst:in std_logic;
     cnt_out:out std_logic_vector(3 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(3 downto 0);
begin
count:process(grst,txclk)
begin
  if grst='1' then
	cnt<="0000";	 
  elsif rising_edge(txclk) then
        cnt <=cnt + "0001";
  end if;
end process;
cnt_out<=cnt;
end counter;
[/code]
 

Re: counter in FPGA

first of all u dont need 8 bits for the count signal ..correct it and then see:)

Added after 1 minutes:

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity counter is
port(txclk,grst:in std_logic;
cnt_out:eek:ut std_logic_vector(3 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(3 downto 0);
begin
count:process(grst,txclk)
begin
if grst='1' then
cnt<="00000000";
elsif rising_edge(txclk) then
cnt <=cnt + "00000001";
end if;
end process;
cnt_out<=cnt;
end counter;
 

Re: counter in FPGA

i checked that too as i have given in next one.
 

counter in FPGA

ur codingstyle is very poor... try this one...and i too am waitingfor what is rong in ur code ..most probably it is the rising_edge function u use...send meur o/p code sequence ...

entity counter is
port(txclk,grst:in std_logic;
cnt_out:eek:ut std_logic_vector(3 downto 0));
end counter;
architecture counter of counter is
signal cnt:std_logic_vector(3 downto 0);
begin
count:process(grst,txclk)
begin
if grst='1' then
cnt<="00000000";
elsif (txclk='1' and txclk'venet) then
cnt <=cnt + "0001";
end if;
end process;
cnt_out<=cnt;
end counter;
there is no way this code wont work ..

Added after 1 minutes:

plz correct the cnt<="00000000" to cnt<= "0000"
 

Re: counter in FPGA

I tried that using "if statement" and "wait until" statement also.
could u/anyone send me some code for counter which works in FPGA.
 

counter in FPGA

that code WILL work...waits we dont use as they r not synthesizable..
 

Re: counter in FPGA

Make sure that ur clock is clean! You might be using switch to generate clock
in that case you need to first debounce the switch!
 

    S

    sanjana

    Points: 2
    Helpful Answer Positive Rating
Re: counter in FPGA

i am using a switch as clock on FPGA but i don't know how to debounce it before using .
could u please tell me how to do it.
 

Re: counter in FPGA

u can m,ake a small separate debouncin ciruitry on a small breadboard and then connectit to one of the fpgas .....
 

    S

    sanjana

    Points: 2
    Helpful Answer Positive Rating
Re: counter in FPGA

Sorry I did not understand. Is there any other way of making a sequential circuit work in FPGA. Is there any other wasy of giving clock to FPGA.
I am at loss how to make a sequential circuit work in FPGA .
could u/anyone please help me
 

Re: counter in FPGA

If possible and just for the sake of illustration you could make a clock circuit (555 clock) and adjust it to a frequency of 1 Hz.

Or you may consider using a signal generator (from your school's lab maybe) and connecting it to the clock pin instead of the switch, this should give you a clean clock signal with sharp edges to trigger your program.

Your program seems to work fine and no big problems, although it seems poor coding (which can be forgiven for beginners like you)

Waiting to hear of your results, and hopefully things will work out well now.
Salam.[/b]
 

    S

    sanjana

    Points: 2
    Helpful Answer Positive Rating
counter in FPGA

Your sequential counter is probably working fine, but it will appear to miscount (or count very rapidly) if you clock it with a bouncy button.

Here's a simple four-button debouncer in Verilog. It's not VHDL, but easy to understand. It requires a clock, but I assume your FPGA board has a clock oscillator.


Are you using a commercial FPGA development board? If you tell us what type board it is, we can probably offer other suggestions.
 

    S

    sanjana

    Points: 2
    Helpful Answer Positive Rating
Re: counter in FPGA

Hi sanjana,
Either use square wave generator or use switch debouncer if ur FPGA Board contains clock generator.

regards
 

Re: counter in FPGA

Thank u for u suggestions . I think this will work.
The kit which I am using is spartan2 XC2S100.It is not a commercial one.
If U know anything about it regarding this please let me know
 

Re: counter in FPGA

becouse you're using the

use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

libraries, then you don't need to vrite 1 as vector.

use simpler
cnt<=cnt+1;

:roll:

also, if you need slow counter...

use the enable in it, and make pulse every second... :)

sth:

process (clk,div_cnt)
begin
if (clk'event and clk='1') then
if (div_cnt(enter yor MSB number)='1') then
div_cnt<=(others=>'0');
else
div_cnt<=div_cnt+1;
end if;
end if;
end process;

the width of div_cnt depends on crystal oscillator frequency... so for 16mhz you need 24 bit's wide...
for 32 mhz it is 25 buts wide, etc etc,

so for you counter

process (clk,div_cnt,key)
begin
if (clk'event and clk='1') then
if (div_cnt(enter your msb value)='1') then
if (key='1') then
cnt<=cnt+1;
end if;
end if;
end if;
end process;

soo, when you press the key, it counts in one second frequency :)

this also shows, that the key is used as enable, not the clock :)

this is called synchronous design, get familiar with it!!!! otherwise there will be some very asynchronous problems :twisted:

hope this help you :)

this one is for you:
h**p://www.actel.com/documents/hdlcode.pdf
 

Re: counter in FPGA

hi sanjana,

please confirm the manufacturer of that kit, or tell me what are the component that are attached to kit, as u had seen on the board

regards
 

counter in FPGA

Hold on, are you sure you reset pin set up high? Are you using dedicated reset pin for the reset? Check reset again.

To do the debouncing circuit on the FPGA you might try lesson two: State machine design....


Regards,


Iouri
 

Re: counter in FPGA

Thank U for u suggestions .finally my code is working in FPGA
 

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