Question in Powerplanning:

Hi all,

Apart from the latest tools which do automatic power grid synthesis, can you all tell something about how it is done manually. I mean how to derive the optimum power mesh and rail dimensions without overusing/underusing the routing resources?

Regards

try synopsys' powercompiler!

Um.. he said no automatic tools.

Hi Dynamicdude,

The latest methodology from Magma could size the power grid to meet your power drop specification.

I think the most important consideration is IR drop in power grid. So if done manually, you can run rail analysis to find out the IR drop. The most difficult consideration is the toggle rate of the net.

It is wise to always over-design the power grid. IR drop affect the speed performance of the gate. It is crazy (at the current technolgy) to take into consideration of the IR drop for every cell to adjust the pin-to-pin delay (which in term change the power drop, and a few iterations is need to get a stable solution, and then OCV and crosstalk noise also shift the delay of the signal ... simply messy). With some over-design, just assume that there is no IR-drop induced cell delay.

Regards,
Eng Han