shakeebh
Member level 2
put a delay in ns in verilog
Here is the code:
module siro(rst, osc);
output reg osc;
input rst;
always @ (rst)
begin
if (!rst)
osc = 1;
else
osc = ~osc;
end
endmodule
I simulated this code on xilinx ise 6.103i through modelsim 5.7g simulator. But surprisingly to me, functional and post-place and route results are quite different. could anyone of u explain why ?
Here is the code:
module siro(rst, osc);
output reg osc;
input rst;
always @ (rst)
begin
if (!rst)
osc = 1;
else
osc = ~osc;
end
endmodule
I simulated this code on xilinx ise 6.103i through modelsim 5.7g simulator. But surprisingly to me, functional and post-place and route results are quite different. could anyone of u explain why ?