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module top (clk, reset, count);
input clk, reset;
output reg [7:0] count;
always @ (posedge clk or posedge reset) begin
if (reset)
count <= 0;
else
count <= count + 1;
end
endmodule
module top (reset, t, n, w);
input t, reset;
input [3:0] n; // any value from 1 through 9
reg [3:0] counter;
output w; // output one pulse of width t for every t input pulses
assign w = ~counter[3] & t;
always @ (negedge t or posedge reset) begin
if (reset)
counter <= 0;
else
counter <= (counter == 0) ? 1 - n : counter + 1;
end
endmodule
echo47 said:thank you very much
The "t" input looks like a clock. You seem to be trying to use asynchronous syntax to do a mostly synchronous job. That can give a variety of unexpected problems.
what problem ? for example? It's better to use synchronous logic wherever possible.
I'm not sure I understand the desired behavior, but how about this?
yesHere's a ModelSim output with n=4, and then changing to n=2:Code:module top (reset, t, n, w); input t, reset; input [3:0] n; // any value from 1 through 9 reg [3:0] counter; output w; // output one pulse of width t for every t input pulses assign w = ~counter[3] & t; always @ (negedge t or posedge reset) begin if (reset) counter <= 0; else counter <= (counter == 0) ? 1 - n : counter + 1; end endmodule
module top (reset, t, n, w);
input t, reset;
input [3:0] n; // any value from 1 through 9
reg [3:0] counter;
output w; // output one pulse of width t for every t input pulses
assign w = ~counter[3] & t;
always @ (t or reset) begin
if (reset)
counter <= 0;
else if (t)
counter <= (counter == 0) ? 1 - n : counter + 1;
end
endmodule