Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Questions of Pipeline ADC design

Status
Not open for further replies.
C

carlyou

Member level 4
Member level 4
Joined
Dec 6, 2004
Messages
78
Helped
2
Reputation
4
Reaction score
2
Trophy points
1,288
Activity points
771
If I want to design a 12bit, 65 or 80MHz pipeline ADC, how can I get the various modules' parameters, such as the sample resolution, OTA gain, and so on, who can give me a advice or introduce some papers? For some reasons, I have to use hspice in windows to simulate my design and only have a TSMC .35 level49 model, is it enough to achieve my aim? Thanks very much.
carl
 

Maybe you can read these papers as following:
‘A pipelined 5-Msample/s 9-bit analog-to-digital converter’
‘Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications’
‘A 10-b 20-Msample/s analog-to-digital converter’
‘Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy’
The author is Lewis and the method of time-interleaved can be included in this project.
 

tsmc 0.35um Process ,, It is a little hard ,
We have implement 80M/12bit pipeline ADC ,
We use 0.18um process , almost MOS we use .35um , but in the critical part we use 0.18um MOS , Like OTA . That OTA can get more high gain . high BW
 

Chung-Yuan Chen said:
Maybe you can read these papers as following:
‘A pipelined 5-Msample/s 9-bit analog-to-digital converter’
‘Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications’
‘A 10-b 20-Msample/s analog-to-digital converter’
‘Indirect testing of digital-correction circuits in analog-to-digital converters with redundancy’
The author is Lewis and the method of time-interleaved can be included in this project.
Click to expand...

want to desig pipeline adc:
by using cadence tool
can u help me or send schematic diagram of each block, darshana26kuche@gmail.com
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top