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How do you simulate the start up circuit for a bandgap?

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Bandgap Design

I need a circuit
 

Re: Bandgap Design

Normally, the bandgap voltage is 1.2V, limited by the bandgap energy of silicon.
Both types viz., voltage are current bandgaps are used in various analog circuits.
One typical application of voltage bandgap is for providing voltage reference for voltage regulator.
Current bandgap is used to generate reference currents for opamps.

For circuits, you can refer any analog circuits book. Use that topology and tweak it for your technology.
 

Re: Bandgap Design

in razavi's analog design book. the opamp plus BJTs works for a 3.3v supply and below.3.3v is a high vdd, i think it not that challenging.
 

Re: Bandgap Design

The books always give just the fundamentals . The rezavi book has even given an architecture for the bandgap.
These architectures need to be tweaked to meet the custom requirements.
 

Re: Bandgap Design

Anyone can explain these questions?




triquent said:
When I let vdd rise from 0V to 2.5V, I got a ripple or spike output about 530mV(stable Vref=1.26V, the spike is 1.79V ). Seems the ripple is too big. How can I reduce the ripple or spike? How to change or compensate the circuit?
hspice2008 said:
I use pwl source ,let vdd rise from 0v to 3v in several ns . then I can see whether the bandgap output can reach its final value without ripple, if have ripple, I will change or compensate the circuits, to eliminate it

in addition , I will run all conners to test the startup of it
Click to expand...

Added after 13 minutes:

when we simulate the bandgap voltage reference, usually we put a capacitance at the output(Vref). Does this capacitance represent the parasitic capacitance? So it is put there just for simulation purpose and for real case? Or it will be implemented by layout?
Click to expand...
 

Re: Bandgap Design

The ouput cap is basically to better the PSRR. More the cap, the better is it.But more cap at the output may interfere with the stability. Just check it out as to what cap value is the best to meet both the worlds.
Normally, it includes the load cap.
 

Bandgap Design

I have some questions:
1.what's the meaning of PWL source?
2.what's the meaning of the process corners?
3.what's the meaning of different PVT?
 

Bandgap Design

PWL source : piecewise linear source
Process corners: Various corner conditions that the fabrication process may take. The poly thichness may vary or intenconnect characteristics may change, or Vt of the transistors may change, with the process.
3. PVT : Process Voltage Temperature. Variations of process/voltage/temperature is called PVT variation.
 

Re: Bandgap Design

"I have some questions:
1.what's the meaning of PWL source?
2.what's the meaning of the process corners? "

your 1st question ans:

i am not sure abt PWL, probably piece wise linear statement used for Front end analog, mixed signal and microwave design .

2nd one...

There are 5 corners according to the threshold voltage variations SS(slow-slow), FF(fast-fast) , SF(slow-fast), FS(fast-slow), TT(Typical-typical).

SS means max Vthp and Vthn
FF means min Vthp and Vthn
SF means Vthp min and Vthn max
FS means Vthp max and Vthn min
TT means intermediate
 
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    woai

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Bandgap Design

I think, the first albhabet in SF/FS/SS/FF correspond to PMOS and 2nd to NMOS.

So, as a correction, to the above message, I say that :

SF : Slow PMOS, Fast NMOS ,i.e, max Vthp, min Vthn
FS : Fast PMOS, Slow NMOS ,i.e, min Vthp, max Vthn
 

Bandgap Design

Mistaking the order between PMOS and NMOS, the right order is showing below:
FS => nmos fast, pmos slow model
SF => nmos slow, pmos fast model
 

Re: Bandgap Design

hspice2008 said:
I use pwl source ,let vdd rise from 0v to 3v in several ns . then I can see whether the bandgap output can reach its final value without ripple, if have ripple, I will change or compensate the circuits, to eliminate it
Click to expand...

Hi Hspice,

Could you please tell your approach to the ripple problem, I mean what are things you look at/change to avoid ripple?


Regards
 

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