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Help about Simulate problem

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M

Matrix_YL

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Hi to all

My verilog module can see test wave and Expected Simulation results is correct in "Simulate Behavioral Model" .
but when I do "Simulate Post-Translate verilog Model" , the Expected Simulation results is quite different

Can you tell what 's wrong with it ?

thank you !
 

Please define "quite different". During post-route simulation you will see all the timing delays and skews, but the overall logic function should be the same as your behavioral simulation, unless you are pushing the chip too fast.
 

    M

    Matrix_YL

    Points: 2
    Helpful Answer Positive Rating
Check for theSetUp/Hold violation Warnings during Simulation. Also, You 'll need to run ur simulation 100 ns and after that apply input vectors. This 100 ns is for Global Set Reset. There might be other reasons too which will need a more explaination of the problem.
 

I want to output my address by A[16:0] when pre_ld_Frame_out is 1 and output 17'bz_zzzz_zzzz_zzzz_zzzz when pre_ld_Frame_out is 0 or output my address after 45ns
when do Simulate Behaviorl Model is ok
do Simulate Post -Translate verilog Model the output A[16:0] always 17'bz_zzzz_zzzz_zzzz_zzzz


I hople you can see my module for more details!
 

if (!pre_ld_Frame_out)
A=17'bz_zzzz_zzzz_zzzz_zzzz;
else
begin
A=address;
#7 DOUT=1'b1;

#45 A=17'bz_zzzz_zzzz_zzzz_zzzz;
DOUT=1'b0;
end
end
Click to expand...

1) Delay is not synthesizable, U might be getting warning for this.
2) A=17'bz_zzzz_zzzz_zzzz_zzzz; => 'll be done
A=address; => 'll be done
U r getting Simulation mismatch as whenever pre_ld_Frame_out=0
A=17'bz_zzzz_zzzz_zzzz_zzzz;
DOUT=1'b0; should be the answer. Is this the case?
 

There are two picture -----> my Simulate results done by Simulate Behaviorl Model and by Simulate Post -Translate
 

OK.. So ur problem if i am getting it correctly is that signal "A" is not updated with "Address" in Post-Xlate simulation. Is it? Well, u just do a simple exercise which can clear ur this doubt & 'll give u more doubts but i can bet it 'll really help U.
You just shift "#45 A=17'bz_zzzz_zzzz_zzzz_zzzz;" before "A=address;" in always@(address) block and do ur simulations.
 

I find this when do Simulate Post-Translate verilog Model

always have these Warnings

WARNING:Xst:854 - "read_a_frame1.v" line 24: Ignored initial statement.
WARNING:Xst:916 - "read_a_frame1.v" line 63: Delay is ignored for synthesis.


I want to know why ? and whether Simulate Post-Translate verilog Model always ignored Delay


Thank you !
 

It's not the simulator that's ignoring the delay statement, it's the physical synthesizer and place-and-route tools. The FPGA/CPLD doesn't contain arbitrary delay lines, so it can't implement your requested delay. This is a fundamental problem. You need to find some other way (maybe a shift register or possibly a DLL) to generate the delay you want.

Those initial statement warnings are frustrating. The FPGA/CPLD *could* implement most initial conditions, but the synthesis tools simply choose to ignore them. Maybe someday the tools will get smarter.
 

echo47 said:
. You need to find some other way (maybe a shift register or possibly a DLL) to generate the delay you want.
Click to expand...

Can you give me some example to implement my module !


thank you very much !
 

I can't give useful examples because they would depend heavily on your existing design, clock rates, chip type, and how far you can deviate from that 45ns goal.

Maybe you have a 20MHz clock. Maybe you can simply pass your signal through one clocked D-flop to get 50ns delay. Maybe 50ns is close enough to 45ns.

Maybe your device contains DLLs. Maybe you can configure one of them to generate a new clock that is skewed from your master clock by 45ns. Maybe you can use it to generate your delayed signal. Maybe the DLL jitter won't cause any trouble.

Too many maybes!

I would try to redesign the timing so everything happens nice and clean on clock edges. That sometimes requires increasing the clock rate.
 

Thank you echo47

I know you means!
I just want to control a SRAM for Read data.The SRAM READ Timing require me to this Delay
I want to use xilinx spartan 2 implement my design !
I can give my SRAM READ TIMING
CE OE UB LB is controlled by state machine so I just use DOUT inform data is ready can get out


if (!pre_ld_Frame_out)
A=17'bz_zzzz_zzzz_zzzz_zzzz;
else
begin
A=address; //when condition satisfied give out address
#7 DOUT=1'b1; //when tOHA is over ,Dout inform data ready

#45 A=17'bz_zzzz_zzzz_zzzz_zzzz; //clear address
DOUT=1'b0; //clear DOUT
end
 

I'm curious why you need to float (set to Z) the address bus. Are you sharing the bus with other devices?

If your SRAM is connected only to the FPGA, then you may be trying too hard to make your signals look exactly like the SRAM data sheet. You may not need to float the address bus, or worry about tOHA, or clear DOUT to zero, or wait exactly 45ns.

The typical way to read from static SRAM is to output the address and control signals on one clock, and then latch the read data on a later clock (after tAA). If you really need to float the address bus, then you can do so at the same time you latch the read data. But normally the only signal that needs to be floated is the data bus, so you can switch from writing to reading.
 

    M

    Matrix_YL

    Points: 2
    Helpful Answer Positive Rating
Thank you echo47

I want to use my FPGA control two SRAMs and same time when one SRAM was reading another SRAM was writing ! when a frame image was grabbed two SRAM'S function change each other

The typical way to read from static SRAM is to output the address and control signals on one clock, and then latch the read data on a later clock (after tAA). If you really need to float the address bus, then you can do so at the same time you latch the read data. But normally the only signal that needs to be floated is the data bus, so you can switch from writing to reading
Click to expand...
Can you give me some examples ?
 

I have never seen a stand-alone example of an SRAM interface. Memory cycle timing is normally merged into the overall project design, so the SRAM interface becomes almost zero lines of code.

Maybe there's a tutorial somewhere that demonstrates basic read/write concepts. Anyone seen one?
 

Hi echo47

module top (clk, clkout);
parameter divider = 25000000 / 400; // must be an even number
input clk;
reg [15:0] count = 0;
output reg clkout = 0;

always @ (posedge clk) begin
count <= count == (divider / 2 - 1) ? 0 : count+1;
clkout <= clkout + (count == 0);
end
endmodule
Click to expand...
I found this in another Post (clock problem),I want to use this module and do some Simulation but same thing happen to me ,this module in" Simulate Behavioral Model" is ok ,but in"Simulate Post-Translate verilog Model" is lost wave clkout=Stx
for see the counter run I specially set count as output!
Can you help me ,for test this module I creat a project and plan to use spartan 2
My platform is ISE7,and modelSim 6.0se
thank you very much
 

Please clarify "is lost wave clkout=Stx". Which "same thing" is happening?

If I understand your changes:
Code: 
module top (clk, count, clkout);
  parameter divider = 25000000 / 400; // must be an even number
  input             clk;
  output reg [15:0] count = 0;
  output reg        clkout = 0;

  always @ (posedge clk) begin
    count <= count == (divider / 2 - 1) ? 0 : count+1;
    clkout <= clkout + (count == 0);
  end
endmodule
I don't have Spartan 2 installed, so I selected Spartan 3 3s50-4-vq100. That works fine here with 100 MHz clock. My post-route sim looks the same as pre-route sim, except of course I now see all the small timing skews. I'm running ISE 7.1.03i and ModelSim SE 6.0c on Win2k.

By the way, I don't use Project Manager. I use command line and a different directory structure. Here is my command for creating the post-route simulation:
netgen -sim -intstyle silent -ofmt verilog -ism build\top -ngm build\top_map -w -dir post

Maybe your clock is too fast? Pre-route sim would not show that problem.

Maybe you need the latest ISE 7.1 service pack. 7.1 is chock-full-o-bugs.
 

Thank you echo47

Let me try again!
for see the counter run I specially set count as output!
 

I see your clkout changing to X. That doesn't happen when I simulate the module that I posted a couple messages ago. My "count" is a module output too.

Please try my module, or show us your code. Also tell us the timescale of your simulation output - you cropped it off your jpeg.

Here's the first few lines of my post-route simulation. The initial 100ns delay is caused by the chip's global reset pulse.
 

Thank you echo47



I knew what's wrong with me! When I use the 40ns of clock timing information so I get wrong result !
when I use the clock as you did 10ns the result same right as you !
`timescale 1ns / 1ps I used , but I still not know why I default value will get wrong result!
fortunately ,I used 146ns get right result !

thank you very much[/quote]
 

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