Difference between FPGA and CPLD

hai everybody,
just now i joined. Let me participate in htese discussions.

i am new to FPGA field. Now i need to port my RTL on to FPGA
for verification.

i feel that, on power up or reset, FPGA becomes empty. it needs to be
programmed every time. but CPLD, once programmed, it retains the logic
even power off or reset.

is it correct. i need clarification.

Re: FPGA Vs CPLD

For FPGA, you can store your bitstream on an external FLASH.

Re: FPGA Vs CPLD

CPLD : (Complex Programmable Logic Device ) A programmable logic device that is made up of several simple PLDs (SPLDs) with a programmable switching matrix in between the logic blocks. CPLDs typically use EEPROM, flash memory or SRAM to hold the logic design interconnections.

FPGA : (Field Programmable Gate Array) A type of gate array that is programmed in the field rather than in a semiconductor fab. Containing up to hundreds of thousands of gates, there are a variety of FPGA architectures on the market. Some are very sophisticated, including not only programmable logic blocks, but programmable interconnects and switches between the blocks. The interconnects take up a lot of FPGA real estate, resulting in a chip with very low gate density compared to other technologies.

The vast majority of FPGAs are SRAM-based, although there are some flash and antifuse versions. The antifuse variety are of interest to aerospace designers because they are more radiation hardened (rad hard).


So basically, there is no difference in between. Often it is diffenciated by size and often defined by marketing reqirement.

Re: FPGA Vs CPLD

Ur are right anjali, In CPLD the design program is stored in the memory even when power goes off, this is same from ACTEL FPGA's

some FPGA's from ACTEL that can also retain the the program in it after the power goes off,

FPGA's from ALTERA, XILINX are RAM based they dont retain the program after the power goes off,

Re: FPGA Vs CPLD

Both CPLD and FPGA has volatile and non-volatile versions.

For dev, CPLD uses the EEPROM versions to store your JEDEC. For FPGA, most come in FLASH.

Anti-fuse is a different story. I think so of you misunderstood. To prevent read-back or IP theft when someone wants to crack your design, anti-fuse serves this prevention purpose.

FPGA Vs CPLD

low size,low speed use cpld
hige size , hige speed use fpga

FPGA Vs CPLD

Their structures are different.
cpld eeprom, fpga sram
so for cpld, you can download your bit file to it.
but, for fpga, you need store your bit file to a eeprom or flash.

Re: FPGA Vs CPLD

Gate density is different.

CPLD: Only 256 Max Flip-Flops can found (Xilinx). 1 Flip-Flop is a macrocell. Clock is only the external to all logics. Max speed 100Mhz

FPGA: > 1K Flip Flops can found, then it have more than 1 Flip-fLop by macrocell, and have a Lock Up Table by macrocell and more, an ALU by macrocell. FPGA have too dual access RAM, PLL or FLL to get any clock inside it. Speed is more than 300Mhz.


It depends how complex is the logic you need to use, to decide if it will fix in a CPLD or a FPGA.

Re: FPGA Vs CPLD

No, the maximum speed of the latest CLPDs far exceeds 100MHz.