What's the best way to study the propagation delays ?

timing question

in the ISE7 in-depth tutorial which is based on a design of a stopwatch,there's something confusing me ....there are two counters being fed with 1 clk source ,first counter has a threshold that will be high exactly when the counter reaches nine,and it will go low in the next rising edge...the threshold pin is connected to the Enable pin of the other counter..the purpose of the circuit is to make the second counter increment by 1 each time the first counter exceeds 9 (tenth and hundredth digits of a stopwatch)

The enable pin will be high at a positive edge for 1 clk cycle and the second counter increments at positive edge also...so,when will the second counter increment?shouldn't there be some phase difference between the enable input and the clk input to ensure that the enable line is high at the clk's positive edge?
I hope my question was clear

timing question

Inside the FPGA or CPLD, the counter outputs change a little while after the clock rising edge. If you study all the internal propagation delays and setup/hold requirements, you will see that the timing works out fine.

timing question

so, the threshold goes back to zero and the second counter increments by one at the same time?

Re: timing question

cmos babe said:

so, the threshold goes back to zero and the second counter increments by one at the same time?

Click to expand...

yes exactly yet the internal delay will handle hold time for the second counter

Re: timing question

What's the best way to study the propagation delays and setup/hold requirements? What ISE tools are used?

Re: timing question

timing analyzer is the best tool in ISE, you can do static analysis on any path you may also include the asynchronous reset/preset signals

timing question

The setup and hold specs for the individual flip-flops are listed in the FPGA data sheet. The routing delays, however, vary with your design, so use timing analyzer to see the overall timing, as bibo1978 suggested.

timing question

Hi,
Yes there will not be any problem as the enable signal is generated only on a particular clock edge and will be sampled by the nest flop only on the next clock edge. Either in FPGA or with discrete components the delays are always more so that there should be no trouble at all.

Best Regards,