DDS implementation in FPGA

anyone has some information about DDS implementation in an FPGA ?

Looking for some kind of tutorial.


Thanks in advance.

implementation of dds in fpga

look at the analog devices site. it have the good dds tutorial.
functional diagrams of dds you can see in ip-cores docs.

dds on fpga

Dear Friend ,
Xilinx has this DDS core to be used as black box in your design .Go to Xilinx IP center
for DDS core . Also if you has Xilinx ISE 6.X/7.X tool , in the Core generator you can get full DDS core and its implementation. Look for Datasheet of this core on

**broken link removed**

dds fpga

Hi

DDS souce code.

Best Regards


Architecture DDS_arch of DDS is

subtype WAVE is STD_LOGIC_VECTOR (5 downto 0);
type ROM is array (0 to 63) of WAVE;
constant SINE : ROM := (
"100000","100011","100110","101000","101011","101110","110001","110011",
"110101","110111","111001","111011","111100","111101","111110","111110",
"111111","111110","111110","111101","111100","111011","111001","110111",
"110101","110011","110001","101110","101011","101000","100110","100011",
"100000","011100","011001","010111","010100","010001","001110","001100",
"001010","001000","000110","000100","000011","000010","000001","000001",
"000001","000001","000001","000010","000011","000100","000110","001000",
"001010","001100","001110","010001","010100","010111","011001","011100"
);
signal frqlt: STD_LOGIC_VECTOR ( 17 downto 0);
signal sum: STD_LOGIC_VECTOR (22 downto 0); --Output of Adder
signal sumlt: STD_LOGIC_VECTOR (22 downto 0); --Output of Adder Latch
signal tblout: STD_LOGIC_VECTOR (5 downto 0); --Output of Gate
Begin



-------------------------------
-- Frequency latch and change
-------------------------------
Process (SetFreq, Reset,Sumlt) Begin
If (Reset = RESET_ACTIVE) Then
frqlt <= "000000000000000000";
ElsIf Rising_Edge(SetFreq) Then
frqlt <= ValeurFrequence;
End if;
sum <= sumlt + ("0000" & frqlt);
End Process;

--------------------------------
-- Latch Adder out
--------------------------------
Process (Clock,Reset) Begin
If (Reset = RESET_ACTIVE) Then
sumlt <= "00000000000000000000000";
ElsIf Rising_Edge(Clock) Then
sumlt <= sum;
End If;
tblout <= SINE(CONV_INTEGER(sumlt (22 DownTo 17)));
End Process;

---------------------------------
-- Get ROM Data and Latch and Output
---------------------------------
process (Clock)
begin
If Falling_Edge(Clock) then
FREQ_SORTIE <= tblout(5);
end if;
end process;

End DDS_arch;

dds core fpga

IEEE
https://ieeexplore.ieee.org/Xplore/DynWel.jsp

you can get you want

ddfs on fpga

bkat said:

IEEE
h**p://ieeexplore.ieee.org/Xplore/DynWel.jsp

you can get you want

Click to expand...

I don't have an IEEE membership :/