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32bit adder in XC95 series

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bamdad

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32 bit adder

Dear all;
I need to implement a 32bit adder in XC95144, I have already implemented it in EPM7128, and the timing analysis shows that it can be used up to 36MHz, and I am using it in 32MHz with no problems. but when I try the same design in XC95144, or XC95288, ISE 7.1 fails to fit the design, or in some cases fit succeeds but the timing analyzer shows that max clock frequency is about 10MHz (I have set a timing constraint of 30ns on the clock period). any ideas?
 

xc95 price

Regardless the project title, I saw many problems in ISE7.1, so that try your design in ISE6.3

Good luck!
 

32 bit adder accumulator

ISE7.1 has a bunch of bugs connected to the XC9500.

Update to ISE7.1.02i and see if it works better.
 

xc95 design

I have tried it in ISE6.1, not 6.3, but the fitter fails to fit. It once did fit the design, but somehow, it seems that the results of the fitter are not reproducable, maximum clocks vary between fits. it seems that ISE tries some sort of logic intensive adder, if it can be forced to use smaller slices, it will succeed, but I don't know how...
 

32 bit adder xilinx spartan3 speed

What error message are you getting? Did the Fitter Report offer any suggestions? Can you show us your code?

A 32-bit parallel adder probably fills up most of that CPLD, especially if you have input registers. I'll bet it goes slow too - the chip doesn't have any fast carry logic.

Try fiddling with the advanced fitting options such as Logic Optimization (speed/density), Collapsing Input Limit, and Collapsing PTerm Limit. It defaults to high speed, which probably causes severe congesion in a 32-bit adder. Be sure you understand what the chip is capable of achieving. (I'm not very familiar with CPLDs.)

ISE is not super smart. Sometimes you have to take its hand and walk it across the street.
 

    B

    bamdad

    Points: 2
    Helpful Answer Positive Rating
carry in adder in xilinx

well, I'm using a very simple code. something like this:

always @(posedge clock)
begin
accumulator=accumulator+control;
end

ISE synthesizes a 32bit synchronous add-sub from this code in speed optimization, and in area optimization, a 32bit ALU.

I've also tried another method:

assign accumulator=result+control;

always @(posedge clock)
begin
result=accumulator
end;

the second code has once fitted with a 22ns minimum clock period, but in other cases, it has failed to fit, saying that the maximum pterm limit exceeded (when trying XC95288) or maximum logic cells limit exceeded (when trying XC95144). the only thing I wonder is that I have tried the EXACT same code, even with more logic for loading the control register in 8 bit segments in 7160 of altera, and even in 7128... why it fails to fit even in 95288?
 

fast carry adder cpld

Complete code please! Need to see your I/O and register/wire declarations.

General rule: don't use = in a synchronous block. Use <= instead.

I built this in ISE 7.1.03i using XC95144-7-PQ160 and all Project Manager settings to default:
Code: 
module top(clk, a, b, y);
  input             clk;
  input      [31:0] a, b;
  output reg [31:0] y=0;

  always @ (posedge clk) begin
    y <= a + b;
  end
endmodule
Code: 
Timing report says:
                          Minimum Clock Period: 8.0ns
                     Maximum Internal Clock Speed: 125.0Mhz
                         (Limited by Clock Pulse Width)

Fitter Report says:

Design Name: top                                 Date:  8- 2-2005, 11:21AM
Device Used: XC95144-7-PQ160
Fitting Status: Successful

*************************  Mapped Resource Summary  **************************

Macrocells     Product Terms    Function Block   Registers      Pins           
Used/Tot       Used/Tot         Inps Used/Tot    Used/Tot       Used/Tot       
65 /144 ( 45%) 514 /720  ( 71%) 249/288 ( 86%)   32 /144 ( 22%) 33 /133 ( 25%)

** Function Block Resources **

Function    Mcells      FB Inps     Signals     Pterms      IO          
Block       Used/Tot    Used/Tot    Used        Used/Tot    Used/Tot    
FB1           3/18       34/36       34          44/90       2/17
FB2          10/18       33/36       33          74/90       5/17
FB3           6/18       33/36       33          68/90       3/17
FB4          11/18       33/36       33          79/90       4/17
FB5           9/18       33/36       33          73/90       3/17
FB6          10/18       32/36       32          67/90       6/16
FB7           8/18       18/36       18          52/90       5/16
FB8           8/18       33/36       33          57/90       4/16
             -----       -----                   -----       -----     
             65/144     249/288                 514/720     32/133

* - Resource is exhausted

** Global Control Resources **

Signal 'clk' mapped onto global clock net GCK1.
Global output enable net(s) unused.
Global set/reset net(s) unused.

** Pin Resources **

Signal Type    Required     Mapped  |  Pin Type            Used    Total 
------------------------------------|------------------------------------
Input         :   64          64    |  I/O              :    96     125
Output        :   32          32    |  GCK/IO           :     1       3
Bidirectional :    0           0    |  GTS/IO           :     0       4
GCK           :    1           1    |  GSR/IO           :     0       1
GTS           :    0           0    |
GSR           :    0           0    |
                 ----        ----
        Total     97          97
<snip>
I'm not sure if that report is telling me happy things or sad.
Could someone with more CPLD experience please jump in here?
 

xilinx 32-bit adder

IO is left for ISE to decide where to place, I have set no constraint on the IO location, but I have placed a 25ns min clock period constraint on my clock signal.
and about the complete code:
I have successfully fit this one in EPM7160 with MaxPlusII 10.2, and the design worked upto 36MHz in timing analysis:

module Adder-Altera
(Address,Control,Strobe,MasterClock,ChAddress,ChLatch,OutputEnable);
input [1:0] Address;
input [7:0] Control;
input Strobe;
input MasterClock;
output [12:0] ChAddress;
output ChLatch;
input OutputEnable;

reg [31:0] Accumulator;
reg [31:0] ChControlWord;
reg [23:0] TempInput;

assign ChLatch=MasterClock;

assign ChAddress=(OutputEnable==1)?Accumulator [31:19]:13'bZ;

always @(posedge MasterClock)
begin
Accumulator=Accumulator+ChControlWord;
end

always @(posedge Strobe)
begin
case (Address)
0: TempInput [7:0]=Control;
1: TempInput [15:8]=Control;
2: TempInput [23:16]=Control;
3:
begin
ChControlWord [23:0]=TempInput;
ChControlWord [31:24]=Control;
end
endcase
end

endmodule


But this one did not fit in XC95144-7TQ100... I messed with the settings of the fitter, and once, and only once did it fit in the chip:

module Adder-Xilinx (Control,Clock,Address);
input [31:0] Control;
input Clock;
output [12:0] Address;

reg [31:0] Accumulator;

assign Latch=Clock;

assign Address=Accumulator [31:19];

always @(posedge MasterClock)
begin
Accumulator=Accumulator+Control;
end

endmodule
 

logic analyzer xc95144

Example A works in Altera, example B doesn't work in Xilinx -- What are you comparing?

Two missing-symbol errors in your second example.

Both examples fit fine in XC95144-7-TQ100. I set fitting option "Logic Optimization" to "Density".

Maybe you need newer ISE or service pack.

Don't use = (blocking assignment) in sequential sections.
 

xc95 clock

both did fit on Altera, none did fit in xilinx... what clock speed did you achive in xilinx? I need at least 40MHz... another point, the second one is simpler, and requires less logic, and I thought it might fit, but it did not, about the missing symbols, they are some sort of typing errors on my side, since both designs can be compiled, there are no synthax or symbol errors here, anyway.
[/list]
 

xc95144 2,54

How can your second example work with Latch and MasterClock undefined?

When I set optimization to "density", both examples fit fine, and report about 6 MHz speed.
To reach 40 MHz, you probably need logic redesign (uncertain success) or a better chip than a 95144.

This goes 21.5 MHz in XC95144-7-PQ160 with default options.
Code: 
module top(clk, a, y);
  input             clk;
  input      [31:0] a;
  output reg [31:0] y=0;

  always @ (posedge clk) begin
    y <= y + a;
  end
endmodule
 

xc95288 example

Please! the second example, it's just a simple mistake... but even if you define those two signals (the Latch signal can be omitted, since it is not a part of actual adder design. and the master clock is simply an input to the adder module...
and my point is that the design does not even fit in 95288... with logic optimization set to balance...
I think that I have to migrate the design in something like spartan 3... in which I can pack more logic... even the processor core :)

BTW, the point is that WHY the first code, which is more logic intensive, fits VERY well in EPM7160, but the second does not fit in 95288 which has more logic? is there any way to force ISE to synthesize some sort of a better adder? I believe that the problem is that ISE does not synthesize a carry look-ahead adder with optimum segment lengths..
 

price xc95

Ok, no more missing symbols, sorry!

Did you try setting fitter Logic Optimization to "density"? You must first enable "advanced" mode to see that option in Project Navigator. After I do that, both of your examples fit fine in 95144, but the clock speed is poor. If I don't set that option, then I have to decrease "collapsing input limit" or "collapsing pterm limit" to achieve fit. Those are both advanced options too. That gave me somewhat higher clock speed, but still nowhere near 40MHz. Have you seen this?
**broken link removed**

Maybe ask Xilinx tech support if they know some trick to squeeze more speed out of a CPLD adder, but I'm doubting it. No fast carry logic, and ISE probably generates an easy solution rather than an optimized solution. Another clue, Xilinx product selector guides don't recommend CPLD for arithmetic applications, and I don't see any suggestions in here:
**broken link removed**

I've never used an EPM7160. It could be a better chip than 95144. Xilinx CPLDs are inexpensive, unexciting. Xilinx FPGAs such as Spartan 3 are vastly more powerful. You'll like it!
 

    B

    bamdad

    Points: 2
    Helpful Answer Positive Rating
32 - bit adder in detail

Yes, the spartan III is astonishing... quite bright in xilinx product line from price AND performance aspect. the only drawback in these new state-of-the-art product families is that one cannot easily interface them to 5V systems, and by easily I mean "by JUST wires". and the older 5V compatible families are more expensive and less featureful. but this is not that much of a concern.

Thanx for your help and time.
 

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