big ratio issue in current mirror

Dear all,
A question on the current mirror. We are designing a circuit whose differetial pair needs the tail bias current of 16mA, which is mirrored from a 20uA PTAT current source. So the ratio of mirror is about 800. I have the concern the small mismatch will be amplified by the big ratio and leads to the big descrepancy of current.

Can anyone have any good ideas to deal with it?

Thanks in advance

John

One way is to look into adaptive biasing technique where we can control the current through the tail current source. But the magnitude you are talking is definately mammoth. Try and use Low Voltage cascode current mirror or a regulated current mirror technique for the tail current source. This is OK if you can go for an extra VDS,sat and if you are not using very low voltages.

Use resistor degeneration in the mirror to improve matching.

With this, you can make parallel and series combinations of transistors and get close results:

Example: Use a unit transistor size of W=500nm and L=5um, and a unit resistor size of 400 ohms.

For the diode connected device, place 25 unit resistors in series (10kohms), and 25 unit transistors in series (effective W/L of .5/125). For the output, place 32 unit resistors in parallel (12.5ohms) and 32 unit transistors in parallel (effective W/L of 16/5)

At 20uA, the voltage drop across the series resistors will be 200mV. At 16mA, the voltage drop across the parallel resistors will also be 200mV.

The transistor ratio would also match the 20uA to 16mA ratio. However, small changes here without the source degeneration resistors would cause significant current error. The degeneration resistors act as negative feedback to supress the variation caused by the transistors.

You could, of course, use an 800:1 ratio, but the method that I gave above will improve matching, since the critical (smallest area) "device" will have more area. Of course, the resistors need to be well matched also, which is why I suggest using many unit resistors in parallel or series, rather than just one long and one short resistor.

Thanks Vamsi and JPR for the useful sugestions.

I'd like to have some further discussion on it. If I did not use the cascode toplogy and source degeneration resistors. I just layout the transistors parallely for the 16mA current path.e.g., I layout them 200x40uA parallely. Then,for these 200 paths, some of them may positively mismath, some of them may negatively mismatch, and it is statisticly. The average of the error can be improved. From this view, the big ratio may not rasie so big concern.

Pls. comment!

John Xu said:

Thanks Vamsi and JPR for the useful sugestions.

I'd like to have some further discussion on it. If I did not use the cascode toplogy and source degeneration resistors. I just layout the transistors parallely for the 16mA current path.e.g., I layout them 200x40uA parallely. Then,for these 200 paths, some of them may positively mismath, some of them may negatively mismatch, and it is statisticly. The average of the error can be improved. From this view, the big ratio may not rasie so big concern.

Pls. comment!

Click to expand...

1. 200 X 40 uA= 8 mA, not 16 mA.

2. One way can reduce the mismatch is increase the length of the transistor to reduce the lamda mudulation effect. Because sometime, it is very hard to get vds the same for both current mirror transistor, by reduce the lamda effect, the transistor will not much depend on vds but just vgs.

Surianova

Simply parallelling the transistors, as you describe, will work exactly as you describe. The impact of 800 parallel transistors will have very little impact on the random offset (approx 28x less than the single device), so will play very little role in the overall current matching. The size will then be almost totally driven by the single diode connected device.

In terms of area (assuming you are limited by matching, not by minimum size), using series connected devices, plus parallel connected devices will need significantly less total area (by probably a couple hundred times smaller for the same matching results) than using the 800 parallel devices, or, for the same area, will probably match by 15x better or more.

The ratio of mirror is about 800 is take large area.
We can not get the good matching .
Used the layout type (1:800) ,the MOS in right ,left,top, down, are not tahe same (process variation)

My suggestion is 40u*200=>40u*10*20 or 40u*5*2 *5*4 . this can reduce area,and improve device matching.