TheBorg
Junior Member level 1
Hi.
I have for some days ago written a subject about using INOUT in a VHDL design, i all got a responce on putting the INOUT bus in 'Z' state before reading, but that i allready had done.
I use the 'Generate Expected Simulation Results' the only two state a can put on is for now '1' and '0', but not read from the bus ?
Any help on the issue is very welcome, a just dont now what to do any more. Source below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( EXT_SYS_Clock : in std_logic;
EXT_SRAM_Data : inout std_logic_vector(7 downto 0);
EXT_LATCH_Data : out std_logic_vector(7 downto 0));
end Counter;
architecture Behavioral of Counter is
TEST: process (EXT_SYS_Clock)
begin
if (EXT_SYS_Clock' event and EXT_SYS_Clock = '1') then
EXT_SRAM_Data <= "ZZZZZZZZ";
EXT_LATCH_Data <= EXT_SRAM_Data;
end if;
end process;
end Behavioral;
Thanks for your help in advance.
Best regards
René
I have for some days ago written a subject about using INOUT in a VHDL design, i all got a responce on putting the INOUT bus in 'Z' state before reading, but that i allready had done.
I use the 'Generate Expected Simulation Results' the only two state a can put on is for now '1' and '0', but not read from the bus ?
Any help on the issue is very welcome, a just dont now what to do any more. Source below:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity Counter is
Port ( EXT_SYS_Clock : in std_logic;
EXT_SRAM_Data : inout std_logic_vector(7 downto 0);
EXT_LATCH_Data : out std_logic_vector(7 downto 0));
end Counter;
architecture Behavioral of Counter is
TEST: process (EXT_SYS_Clock)
begin
if (EXT_SYS_Clock' event and EXT_SYS_Clock = '1') then
EXT_SRAM_Data <= "ZZZZZZZZ";
EXT_LATCH_Data <= EXT_SRAM_Data;
end if;
end process;
end Behavioral;
Thanks for your help in advance.
Best regards
René