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Transaction Level Modeling

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Hi guy,

I try to model something in SystemC TLM but I 've understood just a litle about TLM. I cannot distinguish what is main difference between SystemC TLM and SystemC RTL ?

Can anybody explain ?
 

TLM means that you should describe your design based on transcations not signals. I RTL coding you have to describe the details of signaling. For example when you want to access a memory for reading, you should specify the following signaling in RTL modeling:
1) Activate the Mem
2) Send Read signal to Mem
3) Send Address signals to Mem
4) Get the related Data

But in TLM, you just write a function like ReadMem(Address, Data).

rgds,
KH
 

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    yesme@

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Thanks for the help,
But what all the things we have to consider when we are going for systemC TLM's, have you any good notes for this so that i can implement. What would be the main applications regarding these TLMs as said above that memory etc
please it would be great if i know these.

thanks
raghu
 

TLM is more abstract than RTL, which shall mainly focus on the subjects of transactions/packets instead of the separated signals. In RTL, if you're familiar with it, you should have a good comprehension that RTL is focused on the description of registers and its signals transfer logics. However, TLM shall lift the modleing level which makes you more easily construct your intent.

TLM shall hide the detailed hardware signalling transfer and its implementation mechansim, so that, to some extent, you're descripting the property of the model instead of the signals trasferring. From this point, you may say this mechanism is based on Transactors/BFM concepts.

For good discussion on this top, you shall the following documents.
 

I remember when i read testbuilder document, it said TLM just Bus function model.
 

somewhat similar, but not complete!

as far as bus interfaces are conerned, this is correct!

However TLM stands for a high-level modeling methodology as a whole!
 

TLM is a modeling method in that the operator communicate themselve by their transactions, not signals.

When you make your design in TLM it means that your design don't have any clock. So it must use transaction-event to establish the communication and synchronization.

SystemC TLM is used full for verifacating the functions of your project but not complete in the term of timing.

That is something after I made my project in SystemC TLM.
 

Simply, as the expression implies : the TLM is based on exressing the aspect of a certain system as a set of transactions. For example, if you are modeling a communication network like a WLAN, you don't need to specify any timing for the packets, you don't need to infer any clock .. you can just write thesupposed packets in an input file, read this file from inside the SystemC TX model, and dump the output of the TX send port in another file (say VCD file). Then see the contents of this output file if correctly the TX has modulated the packets and so on.
In RTL, you can't do just this .. you need to specify the clock, reset, enable, registers, .. etc. This is what RTL for.
 

Hi I'm Noor,
New to this group. Basically we will Transaction Level Modeling for the Bus interfaces like we have AMBA,OCP etc. Here we will have transcations rather than signals. A transaction will inturn consist of transfers.

TLM approach is very fast and and we can model a huge platform with this.

with regards
Md.Noorulla
HCL Technologies,Noida,India
 

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