Next step after timing analysis

Hello everybody,

I Have synthesized my code, with few timing constrains, and got the edif netlist file, now if there are critical path's we try to optimize accordingly adjusting the timing constrains, is this right or any other way we need to minimize the critical path. I am using Leonardo spectrum, As the constrains are in our hand and other optimizing technices the tool automatically does. what i have to do at this stage? please help me regarding this.

Thanking you
Raghu

eeeraghu,

Once you have the netlist, check if the netlist meets your timing constraints i.e. setup/hold. You mentioned your design has critical path - every design will have a critical path, what you have to do is check if this path is meeting your timing constraint. If yes - then job done, go to the next stage. If the path is failing timing, then you have to see its failing by how much. Typically small violations (within 10% of your clock cycle) can be fixed by trying more aggresive or advance optimization. For large violations, you may want to fix it by re-writing the HDL or changing the timing constraints. You should not change the constraint just because you are not meeting timing. That should only be done as a last option or if your timing constraints are inaccurate.

Hi SR66

Thanks for that, But i am confused i have a group of critical paths around 10, now i have to select first the longest critical path(with longest delay) right? then it mentions delays between flip-flops comb and wire delays etc, now how to check the set up and hold time violatins ?

And if the critical path report specifies
There are no paths that violate user specified options or constraints, then is it ok and i can move to the next step?

Thanks again
Raghu

you have to check through critical paths only

asic design is a iterative process. you must do according the design flow.

eeeraghu said:

Hi SR66
Thanks for that, But i am confused i have a group of critical paths around 10, now i have to select first the longest critical path(with longest delay) right? then it mentions delays between flip-flops comb and wire delays etc, now how to check the set up and hold time violatins ?

Click to expand...

Are you asking what the specific Leonardo command to view setup/hold violations is? This is usually the default violations report.

If you have violations, you may need to adjust the synthesis effort, or try different synthesis strategies such as flattening. Ultimately, though this can only achieve so much and you may need to modify your design to meet timing requirements if you've tried to synthesize a 64-bit multiplier at 5Ghz in 0.35um process...

And if the critical path report specifies
There are no paths that violate user specified options or constraints, then is it ok and i can move to the next step?

Click to expand...

As long as your constraints are fully specified, yes, then it is OK. It is always a good idea to run the synthesis's tools checking commands to see if any paths are unconstrained, as well as a manual review of the constraints.

Hello eeraghu,

Once you have several paths that violate the timing requirements here is what you do.

1. Make sure you have identified and defined your false-paths (e.g. all paths between 2 asynchronous time domains, multi-cycle is also a false path, reset, and others that are obvious from your design).
2. Identify the Mult-cycle paths.

Indicate these 2 and then get timing reports. That should reduce the # of violating paths.

Then you get PDEF from layout tool if you are doing Physical Synthesis. Then do CTS at your Layout, back-annotate (SDF, SPEF) and then run timing reports again.

good luck