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Can we define the io pad in netlist through UCF file? We are giving the IO pad before generating netlist according to the tool guidelines what about after netlist.
it better to insert IO pads after synthesis into the netlist. better not to synthesize the IO PADS along with your design. It is better to synthesize the design and insert IO pads using some scripts or manually into the generated netlist.
if you write precision constraint of you chip external environment, such as driving ability, load, and voltage level, you can insert IO in synthesis. But frankly, i never use it. It is better to add IO cell in your RTL and in the top level of your design. It must fit your dirving requirement. During synthesis, you only compile the level under IO cell level, and write out netlist of whole chip. Tools will not modify your IO cell.
It is good design practice in your RTL to have any given RTL block either purely structural or purely behavioural, and not to mix the two. Therefore, use a separate level of hierarchy to instance IO pads if you are doing it in RTL.
Yes hgby2209 is right, even though we define io pads and other delays, at synthesis level it does not see. these come into the picture while implementing or mapping.
I also favor using a top level RTL file to put the I/O cells including input registers and output registers. I also instantiate the cells to make sure I get the right cell type and drive I need. This is good place also to put the cell placement constraints. I use a separate timing constraint file for the top module and the core, this way the I/O interface and the core timing requirements can be specified separatly.
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