Oregano's mc8051 VHDL Core .. NOT WORKING !

mc8051 core

Hi guys ..

Anyone used Oregano's mc8051 VHDL core before ? .. Anyone stimulated/tested it with a real 8051 program out of Keil for example ? .. I guess there is a problem in the core .. it forbids u from writing in the internal memory range (128 -> 255) completely .. it doesn't only menace u from writing irrespectively, but it allows you not to write at all ..

for example, if you want to execute this instruction :

MOVE AA, #20H

the write enable of the internal RAM doesn't go high to enable the writing to the location (AA) ..

So, anyone encountered this before ?

mc8051

Hi omara,
yes thats true. If you look at the core source code, you will understand that. The core defines only 128 bype of internal RAM. Actually the problem is that this is an 8051 core and not an 8052 one. 8051 only allows accesing of internal RAM from 0-127 bytes. 8052 allows access for 128-255 bytes, only through indirect addressing. So you cannot write data in a address say "AAh". One more thing you try to pick any 8051 type target in Keil and try to load "AAh" with data, that will also forbid you from writing. Hope this helps. Do reply if any further doubts.

Best Regards,

oregano sfr

dBUGGER said:

Hi omara,
yes thats true. If you look at the core source code, you will understand that. The core defines only 128 bype of internal RAM. Actually the problem is that this is an 8051 core and not an 8052 one. 8051 only allows accesing of internal RAM from 0-127 bytes. 8052 allows access for 128-255 bytes, only through indirect addressing. So you cannot write data in a address say "AAh". One more thing you try to pick any 8051 type target in ke*il and try to load "AAh" with data, that will also forbid you from writing. Hope this helps. Do reply if any further doubts.

Best Regards,

Click to expand...

Hi dBUGGER
8051 has an internal physical RAM of 256 , and not 128. Yet, you only use the upper 128 while the lower 128 are considered the SFR area. Oregano's core should allow you to write to those SFRs, but effectively I don't think it allows u to .. I tried to write to the stack pointer (SP) using its assigned instruction, and it didn't work with me. Did it work with u ?

Second thing, if you use Keil, u can use Oregano's core itself as a target. Yet, the behavior of the assembly code on keil will be different from that of Oregano's VHDL code when u run the same program on both.

Any comment or different expereince ?

oregano sfr control_mem.vhd

Hi omara007,
I have tried writing to SFR locations like IE, IP, P1, P2 etc. and it all worked. As far as SP is concerned i will check that and let you know.

Best Regards,

dBUGGER said:

Hi omara007,
I have tried writing to SFR locations like IE, IP, P1, P2 etc. and it all worked. As far as SP is concerned i will check that and let you know.

Best Regards,

Click to expand...

U tried to do that on VHDL ? .. or Keil ?

I need u to do something else .. to try to write to an internal RAM location between 128 and 255 but not assigned to an SFR. Please if u do, just notify me with ur output.

Hi,
As i told you previously also, you cannot write to internal RAM in the range 128 - 255. Only SFR with the matching addresses can be written. You don't get confused between an 8051 and 8052. Any standard 8051 has only 128 bytes of internal RAM and the upper 128 bytes are mapped as SFR addresses. So it is correct that it does not allow to write in internal RAM locations from 128-255. Just try that in keil, It will give some error stating "no execute read/write permission". I have checked the basic functionality of the core in keil and through Xilinx. And i found it working !!! Hope this helps. Please do reply if any your doubts are not clear.

Best Regards,

dBUGGER said:

Hi,
Only SFR with the matching addresses can be written.

Click to expand...

How did Oregano implement the SFRs ? and in which VHDL module ?

Hi omara007,
Oregano implements SFR as simple 8-bit registers. They all are implemented in control_mem.vhd file. Go through that file and you will understand how.

Best Regards,

dBUGGER said:

Hi omara007,
Oregano implements SFR as simple 8-bit registers. They all are implemented in control_mem.vhd file. Go through that file and you will understand how.

Best Regards,

Click to expand...

I saw the registers now .. there is one problem .. in any text book, if you go for 8051 physical internal RAM u will find it 256 .. again am not talking about 8052 .. I know what am saying .. it's 256 of physical RAM .. only 128 is accessable by the programmer .. while the other 128 portion is defined as the SFR regio .. for this you can say P0 address is 80H .. right ? .. or how come it's 80 as long as it's not RAM location !!! ..
P0 -> 80H
TCON -> 88H
PSW -> D0H
and so on ..

So , the problem lies when u try to access these SFPs with their native address .. can we do that ? .. like (MOV 80, #0x00H) ? ..

What if I wanted to define some SFR for my own use ? .. and on the papers I put their address as A4 for example ... in this case I will need to do major changes in the VHDL code .. like desiging a decoder for this address to select this register instead of easily deal with it as a memory location ..


U have any comment ? .. I do really appreciate ur help ..

Hi omara007,
I think we misunderstood each other. It is true that we can access only 128 bytes of internal RAM but wether the inside the chip it is 128 or 256 bytes is not known. Regarding the SFR registers they can be defined as simple 8-bit registers but will respond correctly to the 8-bit direct address because the address is mapped like that. So in Oregano core they have not provided the upper 128 bytes of RAM as such coz it can never be used. Again it is their way of defining things. Maybe someone else can write in some other way!!!
As you asked wether writing MOV 80h,#00h will write "00" to port 0, answer is YES it will.
If you want to define your own SFR address then yes you will need to add the code for that in the required "case" statements. That is not wrong as other SFR's are also decoded like that.
The other option is to extend the SFR bus out. Then in your external modules you define the other SFR's whichever you want to with some address that does not conflict with the existing SFR's.
Hope i was clear

Best Regards,