Why read and write pointers are gray encoded in FIFO design?

asychronous fio design

I want to know why in the asynchronous fifo design , the read and the write pointer is gray encoded?

Re: asychronous fio design

because read clock and write clock are asynchronous,

write address is generated in write clock domain,

read address is generated in read clock domain. in asyn fifio,

we need to compare write address and read address to

determine empty and full flag as well as how many bytes

are in fifo. so we must pass write address to read clock domain

and pass read address to write clock domain.

if read address and write address is not encoded in gray code,

address will has many bits to change, that will lead

wrong address. because we can't pass multi-bits data

across asynchronous boundary reliablely.

by using gray code, this problem is solved.



best regards

dak-ju said:

I want to know why in the asynchronous fifo design , the read and the write pointer is gray encoded?

Click to expand...

asychronous fio design

Hi,
It is done to get rid of the problem of multiple bits synchronization. With Gray encoding only one bit changes at a time so a simple synchronizer circuit can be used to synchronize the pointers from one domain to another.

Best Regards,

asychronous fio design

To further simplify dBUGGER, all bits in a signal are unable to change in a single shot of time, and it might result in Glitches. In Gray encoding, only a single bit changes so u need to synchronize only one bit.

Re: asychronous fio design

another method can be used: the asynchronous comparsion of the write pointer and read pointer. the pointers can be implemented using one-hot or gray code to reduce the unnecessary bit transistion so as to reduce the possibilities of the comparision signals represneing the status of FULL or EMPTY. Of course, the FULL or EMPTY shall be sampled by the other clock filed clock to generate the error signal. The synchronous FULL_s and EMPTY_s and Error_s shall be generated with a syncronizer to get rid of the metastability.

There are many articles describing this topic and you can search on the google.


Good Luck!

Re: asychronous fio design

Gray codes are used in such case because the empty and full conditions are defined by comparison between the FIFO read and write pointer, however the read and the write process run on different indpendent clocks, if the comparison is made between binary counter false glitches might occur because of data skew to the comparator and because more than one bit might change (for example if you have a four bit counter the transition between 15 and 0 will result the all four bit changes, and because of the skew any value might be seen by the comparator depending on the skew) this might result a false alarm because the read and write clocks are independent it migh occur that this false alarm is captured by the other clock domain, for example if you have the above transition occurs during a read process the glitches might be registered by the write process, introducing a false alarm which in this case might be a full flag.
Other encoding techniques might reduce this propability like one-hot encoding but still with one hot a two bit transition occur which still might introduce a glitch the safest way is to use a gray code.
It is noticeable that with such technique the full or the empty flag deassertion might occur one clock later relative to its clock domain (full is a write clock domain signal, empty is a read clock domain flag) and intutively this is not a big deal,(i.e. you might stay for a clock cycle for a write process while a the fifo is not full or you might stay for a clock cycle for a read process while the fifo is not empty).
still you have to make sure to avoid the metastability by inserting filters in the clock domain whit the appropriate direction of flag motion, for example an empty flag deassertion process (write clock doamain process to a read clock domain flag) should include a metastability filter.
However I prefer that you do it in both ways yet it depends on your design.

that's all folks

Re: asychronous fio design

Nice Discussion friends I want verilog code for writing and reading logic of fifo

Please provide me the same and/or give me the guide lines to devlop..

I am a starter please help me.

I have some basic concepts on fifo