Verilog codes for clock divider

module clk_div(clk_50mhz, rst_n, clk_60hz);
   input clk_50mhz, rst_n;
   output      clk_60hz;
   reg         clk_60hz;
   
   reg [47:0]  counter;

   always @(posedge clk_50mhz or negedge rst_n) begin
      if (!rst_n) begin
         counter <= 48'h00000;
         clk_60hz <= 1'b0;
      end else begin
        if (counter == 48'h65B9A) begin
           counter <= 48'h00000;
           clk_60hz <= ~clk_60hz;
        end else begin
           counter <= counter + 1'b1;
        end
      end // else: !if(!rst_n)
   end // always @ (posedge clk_50mhz or negedge rst_n)
endmodule // clk_div

If you need a slower clock, here is a simple clock divider algorithm, that divides the clock by 2N.

Where :

N = f(clk) / (2* f(desired))

 

-- file "clk_div.vhd"

-- a generic clock divider, divides by 2*N

-- adapted from "VHDLL Primer" by J. Bhasker, p. 295

------------------------------------------------------------------------------------------

  
library ieee; 
use ieee.std_logic_1164.all; 
  
entity clk_div is 
  generic(N: positive:= 2); 
  port 
    (fast_clk, reset: in std_logic; 
     slow_clk: buffer std_logic 
    ); 
end clk_div; 
  
architecture behavioural of clk_div is 
begin 
  process(reset, fast_clk) 
    variable count: natural; 
  begin 
    if reset = '1' then 
       count := 0; 
       slow_clk <= '0'; 
    elsif rising_edge(fast_clk) then 
       count := count + 1; 
          if count = N then 
             slow_clk <= not slow_clk; 
             count := 0; 
          end if; 
   end if; 
  end process; 
end behavioural;

process(clk_50mhz, rst_n)
  begin
    if reset = '0' then 
      ........
   elsif rising_edge(clk_50mhz) then   
      .......

module top (clk, hz60);
  input             clk;
  reg        [21:0] count = 0;
  output reg        hz60 = 0;

  always @ (posedge clk) begin
    count <= (count == 2499999) ? 0 : count + 1;
    hz60 <= (count == 0) | (count == 833333) | (count == 1666666);
  end
endmodule