[Verilog] How to read data from a file?

Hi all,

I want to read one data per clock from a flie, and send them to a pipelined circuit.
After that, save one data per clock to a file.

I am new to testbench. Now I decide to read a data (in) from file @(negedge clk).
And pass this data to the module that I want to test @(posedge clk).
After that, save data (out) to a file.

Is my test method right? Any suggestions will be appreciated!

// Code list below seems not work
//------code-----------
`define clk_cycle 10
module testbench_tb;

reg gclk;
integer os1,os2;
integer i,j;

wire [5:0] in;
reg [5:0] out;

initial begin
gclk = 0;
os1 = $fopen("tb_1.txt","r");
os2 = $fopen("tb_2.txt","w");
end

always # (`clk_cycle / 2) gclk = ~gclk;

always @ (negedge gclk)
begin
$fscanf(os1, "%d", in);
$fwrite(os2, "%d", out);
end

// pipelined circuit under test
always @ (posedge gclk)
begin
if(greset == 0)
begin
out <= 0;
end
else
begin
out <=in;
end
end
endmodule

Best regards,
Davy

Use $readmemb or $readmemh to load a reg array (memory) with file data.

$readmemb — The file contains binary ASCII data

$readmemb ("filename", memory_name, [start_addr, [finish_addr]]);

$readmemh — The file contains hexadecimal ASCII data

$readmemh ("filename", memory_name, [start_addr, [finish_addr]]);

You can default the addresses, or provide them in the system task or in the data
file (or both). The system task by default writes from the left memory address (as
declared) toward the right memory address. Addresses (if any) in the data file
must reside with the range (if any) specified in the system task.

this might help u,

It is obligatory that be couple the task $fopen and the task $fclose, Only $fopen, you will occupy the deal with memory.

hi, davyzhu
You can declare two large reg arrarys as input/output buffer.
If your input data is in ASCII format, use $readmem* as eeeraghu's describption. Otherwise use $fgetc in initial block.
Then save the data in output buffer to file before $finish.

Regards,
Jarod