how a LATCH is different from FLIPFLOP?

I TRYING TO FIND THE REAL ANSWER FOR A LONG TIME. TILL NOW IT IS HARD NUT TO CRACK FOR ME

from the book

hope it can clear ur doubt....

regards,
sp

flipflop and latch are basically same but flipflop is clock driven but latch is simple array of register.both r used alternatively.

The main difference between a latch and ff is the way they changed their states.FF uses clock signal to change their output where as latch have a control input ,according to which user can change latch's o/p state.

LATCH is asynchronous .(there is no clock)
flip flop are SYNCHRONOUS with a clock

eltonjohn said:

LATCH is asynchronous .(there is no clock)
flip flop are SYNCHRONOUS with a clock

Click to expand...

If i decided to connect the enable to a clock siganl what will be the result , you may say lath is trasparent , but all level triggerd flops are also transparent , can i call level triggered flip flop as latch ,

Latches are level triggered devices while FFs are edge triggered

Another aspect is that latches are usually used to store data words. That is why they come in multiples of 8 in a single IC package and sometimes have tri-state outputs.

Latches seldom have preset and clear and if they do, there is just one input for all of the bits. Flip flops always have set and clear for each bit.

Flip flops are usually used in computational circuits to store one bit of state information. One example is a sequential logic circuit. Another is as a simple frequency divider. Another is in a phase detector.

Basically, latches are in fact just flip-flops, but intended to store or "latch" the data present at the inputs before the clock edge.
Therefore, latches generally lack the /Q output and are implemented as D FF.

Flip-flops generally have both outputs available, as well as clear an possibly preset inputs, and are intended for other uses, such as frequency division and sequential logic implementation. FFs can be of the JK variety, too.

you can construct a flipflop from a latch.
latch is precisely a level triggered device.flipflop is an edge triggered device.
to construct a positive edge triggered flipflop, take two latches.
first is negative level triggered and the second is positive level triggered.
connect them in series.

I forgot to say that latches, if they do have a tristate, set, or reset control, it is common to all of the bits. The same goes for the clock input. Flip flops have all of these controls individually for each bit (or flip flop).

Here is a piece of history. Back when TTL was just plain and not LS or other variants the 7474 flip flop as manufactured by Texas Instruments had a defect. If the input went high and then back low, the next clock signal would put a high on the output. This was independent of any setup or hold times. Some products were designed to take advantage of this effect. Then when the 74LS74 came out this error was fixed and people who substituted this version for the 7474 in their designs had defecttive products.

There is so much conflicting statements here, and many more in texts.

I was told that flip flops were unclocked suck as an R-S and J-K. Latches are basically flip-flops that are clocked. If you look at the D-Latch, you will notice that it is a J-K flip-flop, with the exception that it is clocked.

But I'm probably wrong, and I haven't gone over that stuff in a while.

The RS is not clocked, the other types are or can be.

1. in IC design, we usually build DFF (Dtype Flip Flop) form two LATCHes which used reverse enable signal (~CLK and CLK).
2. LATCH is level triggered. the equation is Q=D*Enable, enable can be any logic signal, including Clock signal.
3. Flip Flop is edge triggered. the equation is Q= posedge (D*CLK)
4. these two cells are all memory cells. Latch is much the same as SRAM, and Flip flop is much the same as REGISTER.

A latch is a memory element, that is level sensitive. It is "set" or "reset" by applying a level to one of two inputs.
~
A flip flop consists of a latch, plus additional circuitry to determine under what conditions the latch will change state. A flip-flop changes state on the rising or falling edge of a clock, depending on the design. In addition to the clock input, a flip-flop provides other inputs to determine what state the flip-flop changes when the clock edge occurs. Examples:
~
R-S Flip flop has 2 control inputs "R" and "S" in addition to the clock. Here are the states to which the flip-flop changes:
~
S Input R Input Next State
0 0 No Change from previous State
1 0 1
0 1 0
1 1 Not allowed, unpredicable result
~
J-K Flip flop has 2 control inputs "J" and "K" in addition to the clock. It is similar to the R-S flip-flop, except the "1" "1" input combination is allowed. Here are the states to which the flip-flop changes:
~
J Input K Input Next State
0 0 No Change from previous State
1 0 1
0 1 0
1 1 Changes state from previous state
~
D flip-flop has 1 control input "D". Here are the states to which the flip-flop changes:
~
D Input Next State
0 0
1 1
~
T flip-flop has 1 control input "T". The T flip-flop toggles (changes state) at each clock transition.
~
In addition, most flip-flops have direct "Set:"and direct "Clear" inputs that cause the flip-flop to change state independently of the clock.
~
I hope this helps.

Latch is level-sensitive.
But Flip-Flop is clock-edged for data storage.

see this

**broken link removed**

Hi,
Latches are level sensitive devices, while flip flops are edge trigered devices.

thanks
sawaak

flip flops are edge triggred devices noremally data is sampled on the positive or negative edge of the clock.Alatch is a level sensitive device.A latch and change its state anytime when the clck is low or high according to its definition in the circuit.

the simple difference between FF and latch is given below.

FF is edge triggered ---means FF output just looks at the data at the rising(falling) edge of the clock and remains same until the next rising(falling) edge of the clock.at next clock it agains looks at the data.

latch is level triggered---means latch ouput totally follows the data between the two clock rising(falling).