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Two Verilog FSM style compare

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davyzhu

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+compare verilog

Hi all,

There is a problem on How to write FSM in Verilog(https://www.asic-world.com/tidbits/verilog_fsm.html).
Most synthesis tools recommend second "Using Two Always Blocks" style. But I would like to use third "Single Always" style. It seems more compact.

What's the pros and cons between the two styles? I see that the third style may have state transition latency. But does the third style gain higher frequency and shorter critical path?
Thanks!

Best regards,
Davy
 

fsm in verilog

You can use any of the three stsyles mentioned depending on your convenience. But its a better practice to have multiple always blocks since it aids in efficient debugging.
 

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    davyzhu

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verilog fsm

As for me, I always use 2 always block. This is because first always block is my state (present n next) and the second always block is my combo logic block.

As we all know, fsm basically, have 2 part.
1. flip flops
2. combo logic

Thus, by using 2 always block it made my life more easier to code and to debug.

But again, "it is depending on your convenience ", masai_mara :)
 

verilog compare

I deem that the style of two block of always is better since it is good at the area and timing!!
 

fsm verilog

Hi
find the attached paper that describes th epros and cons of the various coding styles
i hope it helps
regards
 

    D

    davyzhu

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fsm coding styles

davyzhu said:
What's the pros and cons between the two styles? I see that the third style may have state transition latency. But does the third style gain higher frequency and shorter critical path?
Click to expand...

I think single always and dual always will have the same performance.
The chip performance is based on your coding style.
If you will gain higher frequency, you can use pipeline architecture.
But dual always approach have more easy debuging.
 

fsm 2 always 1

I usually use three always blocks to describe a finite state machine.

one block is sequential logic;
second block is next state combinational logic;
third block is output logic.

I feel this style is very clear and ease to debug.

for synthesis, I think all style will be same, because

DC is clever enough.

best regards




davyzhu said:
Hi all,

There is a problem on How to write FSM in Verilog(h**p://www.asic-world.com/tidbits/verilog_fsm.html).
Most synthesis tools recommend second "Using Two Always Blocks" style. But I would like to use third "Single Always" style. It seems more compact.

What's the pros and cons between the two styles? I see that the third style may have state transition latency. But does the third style gain higher frequency and shorter critical path?
Thanks!

Best regards,
Davy
Click to expand...
 

HI,
refer to cummings papers. Even three always block can be reduced to two with the o/p encoded with the state. In this case two always bocks else three will be good.
best Regards,
 

whether you use 1, 2 or 3 always block, the synthesis result should be the same. 2 or 3 always block should be good as it provide better readability to the rtl code. i used to usse 3 always block but later when design get bigger and more states to code, change to 2 as easier to track and trace state and outputs.
 

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