lna@2.45GHz integrated circuit

i am a beginner of RFIC,i have designed a lna at 2.45GHz with charter's kit. now i have been simulating it with Spectre RF, i have swept C-S MOS's width and other parameters, NF is always 2.7dB, but after determining these parameters, i swept frequence , a null of NF about 2dB is around 1.8GHz, certainly at 2.45GHz ,the NF is still 2.7dB. i have try to change the width of input MOS,but the null is hard to move to a point of 2.45GHz. i don't know why it is???
my topology is traditional , cascode with source inductor degeneration!
thanks!!

How about your NFmin v.s. frequency??

what relationship between them??
NFmin vs. frequency should be what??
could you explain it in detail?? thank you very much !!

The NFmin v.s freq. plot should looks like a bowl, it indicates the minimum NF value an LNA can achieve at specified freq.. Read more about the following topics: Noise match, device noise model. And Gonzalez's book is recommanded.

and I guess chartered's PDK uses BSIM 3.3 MOS models
so T.Lee's formula is not so applicable now

To:sgperzoid
what do you mean?? why???so.... I can't follow his formula?? then which one can i follow?? i am confused!!
if the NFmin is correct, the phenomenon is why??

thank you very much

Added after 7 minutes:

To:dsjomo
when i sweep the width of C-S MOS, the bias current is changed , how is it affect the quality?? what should i do ? is this having a connection with the phenomenon as i said early???

I mean that the T. Lee's formula is only applicable for library that uses BSIM4 MOS model, while I think Chartered's model is BSIM3.3, which does not take the gate-induced noise into consideration.
So you can not get the optimum noise performance at the optimum width in the simulation.
However, I think you can still get a minimum NF because of exsitance of optimum noise matching.

The only thing you can follow is the measurement result of your testkey device. The formulas only gives you an idea about how the phenomenon occurs.

If the NFmin is correct that means the simulation process is correnct. You have to learn the method by which the microwave engineers design their LNAs. They don't use small signal equivelant model to design the LNA, however, they did almost everything on Smith chart.

Fix power => sweep width
Fix width => sweep power
Fix power => sweep width
Fix width => sweep power
Fix........
Repeate these steps to find a local optimum point.

To:sgperzoid
As you said "So you can not get the optimum noise performance at the optimum width in the simulation.
However, I think you can still get a minimum NF because of exsitance of optimum noise matching"
could you expain them in detail. why i can't get the optimum noise performance but i can get a minimum NF??

Added after 9 minutes:

To:dsjomo
as you said " Fix power => sweep width" , when sweeping width, the capacitor of M1 is changing,so the match condition has shifed, should i sweep the Lg simultaneously???
and i want to know the standard of noise matching?? power matching can be achieved through monitoring S11, but noise matching through what??
i am a graduate, how can i find the way by which microwave engineer design their LNAs??
thanks

tiger_ads said:

To:dsjomo
as you said " Fix power => sweep width" , when sweeping width, the capacitor of M1 is changing,so the match condition has shifed, should i sweep the Lg simultaneously???
and i want to know the standard of noise matching?? power matching can be achieved through monitoring S11, but noise matching through what??
i am a graduate, how can i find the way by which microwave engineer design their LNAs??
thanks

Click to expand...

I guess that you've read Shaeffer's paper, thoroughly. At last stage of NF optimization, the problem shrinks down to find the optimum point of P(PD,ρ). It is a 2D optimization. PD represent for the power consumption while ρ represents for the device dimension.

The above optimization process is focus on device characteristic, you can't find Ls, Lg or any element related to matchin in those formulas except a given Rs.

While we power match the device according to its s-parameter, we noise match the device with its Γopt value.

Read this book:
"Microwave Transistor Amplifiers" by Gonzalez
I remember someone has upload this book before, check the upload forum plz.

To:dsjomo
you're right, i have been doing this job following Shaffer's paper"A 1.5-V,1.5-GHz CMOS Low Noise Amplifier" i am involving in RFIC, so i can't know the device's S-parameter, only through SP simulation, and could you expain your noise matching in details?? my english is a little poor, i am sorry

and the attachment is my result NF(NFmin) vs.frequency, is it right?? my working frequecy is 2.45GHz. but the minimum of NF is around 1.9GHz(first diagram). The second one ,i have use a ideal inductor instead of part of actual inductor. the ideal one is continuous changing, and the actual one is discrete. so i can sweep the ideal one , and the result is improved a little, the minimum of NF is moving towards 2.45GHz.

NFmin increases as frequency is raising, is it right???

tiger_ads said:

To:sgperzoid
As you said "So you can not get the optimum noise performance at the optimum width in the simulation.
However, I think you can still get a minimum NF because of exsitance of optimum noise matching"
could you expain them in detail. why i can't get the optimum noise performance but i can get a minimum NF??

Added after 9 minutes:

To:dsjomo
as you said " Fix power => sweep width" , when sweeping width, the capacitor of M1 is changing,so the match condition has shifed, should i sweep the Lg simultaneously???
and i want to know the standard of noise matching?? power matching can be achieved through monitoring S11, but noise matching through what??
i am a graduate, how can i find the way by which microwave engineer design their LNAs??
thanks

Click to expand...

Simply because the MOSFET model u r using is BSIM 3.3, which does not model the gate-induced noise.
You can still get a minimum noise figure in your simulation due to optimum noise matching considering only the channel thermal noise. But the result must deviate from T. Lee's theory


regards

do you think my simulation result "NF(NFmin) vs. frequency" is correct??
it is in my last time reply' attachment
thanks a lot

It is quite common if the optimum NF point occurs at freq. other than input port power matched freq. But the position of this freq. is not helpful for our design procedure because we do not know the relationship among this freq. and other parameters like device width, bias current, etc.

To say it clearly, the problem why you can't simutaneouly match on power and noise is because that the transistor is a active device, its input referred noise sources vn and in are correlated. Source degeneration can change the S11 while keep the noise performance almost unchanged, i.e it change Zin while keeping noise performance unchanged.

Added after 21 minutes:

sgperzoid said:

Simply because the MOSFET model u r using is BSIM 3.3, which does not model the gate-induced noise.
You can still get a minimum noise figure in your simulation due to optimum noise matching considering only the channel thermal noise. But the result must deviate from T. Lee's theory


regards

Click to expand...

It is very very interesting that, if you find the NF eq. derivation page of Shaeffer's PH.D paper (i.e, T.H.Lee's paper... ), you'll see that, the NF is mainly composed of 4 terms. One term is a UNITY ONE, this is the dominant part. The rest parts are composed of one complicated term, and two other term (Rg/Rs) and (Rl/Rs). And then, Shaeffer said that the last two terms are negliable so he drops the two term from the beginning. But as we get the final NFmin value at some few pages later, we find that the NFmin is sligtly greater than 1. That means the complicated term is small also.

The problem is, when we try to make a commercial LNA, the input is preferred to 50ohm, that means the (Rg/Rs) and (Rl/Rs) is larger than one might think thus IT CANNNNOT BE NEGLECTED. Before the release of BSIM4, somebody tried to fix BSIM3 to get a good performance. Maybe you can still find some paper on IEEE today that talking about how to improve BSIM3. But none of them inserts the INDUCED gate noise source into the BSIM3 model. All they did is just adding some R and L around the 4 terminals.

Because the measurement environment are 50ohm everywhere, so the Rs is 50ohm with no doubt. And this minimize the active device character dependent term in NF, leaves (Rg/Rs), (Rl/RS) and UNITY. So, no doubt we'll get a better noise performance, especially the Rg is higher at that time. Because at that time, the line width is greater than 0.35um.

i am very very appreciated for your help!! i think your suggestion is very helpful, but i have not understanded your mean due to my knowledge about this field and poor english level. could you explain it in Chinese to my e-mail??

do you see my attachment about my simulation results before??? i want to know whether it is reasonable, because this my first work on RFIC, thank you very much!!

my e-mail address: tiger_yz@hotmail.com

tiger_ads said:

i am very very appreciated for your help!! i think your suggestion is very helpful, but i have not understanded your mean due to my knowledge about this field and poor english level. could you explain it in Chinese to my e-mail??

do you see my attachment about my simulation results before??? i want to know whether it is reasonable, because this my first work on RFIC, thank you very much!!

my e-mail address: tiger_yz@hotmail.com

Click to expand...

I'm afraid that I don't have much time to translate my words. If you are a student, i think you have to learn how to work independently. I can give you resources and directions, but you have to study every detail by yourself. But I won't charge you a dollor for being a consultant because you are still a student. We can discuss, but you have ask first.

The goal of education is not focusing on how to train a person with professional skills. Instead, it trains us how to face unknown problems.

Added after 1 hours 25 minutes:

tiger_ads said:

i am very very appreciated for your help!! i think your suggestion is very helpful, but i have not understanded your mean due to my knowledge about this field and poor english level. could you explain it in Chinese to my e-mail??

do you see my attachment about my simulation results before??? i want to know whether it is reasonable, because this my first work on RFIC, thank you very much!!

my e-mail address: tiger_yz@hotmail.com

Click to expand...

Those simulation curves are reasonable.

my understanding is that because Rs is 50ohm, so the term Rg/Rs and Rl/Rs can't be inegligible, and the active device character dependent term in NF is not dominant. is it right??
but what's your mean "no doubt we'll get a better noise performance, especially the Rg is higher at that time. Because at that time, the line width is greater than 0.35um." could you expain it clearly?? thanks

could you suggest something according to my simulation plotting?? thanks

tiger_ads said:

my understanding is that because Rs is 50ohm, so the term Rg/Rs and Rl/Rs can't be inegligible, and the active device character dependent term in NF is not dominant. is it right??
but what's your mean "no doubt we'll get a better noise performance, especially the Rg is higher at that time. Because at that time, the line width is greater than 0.35um." could you expain it clearly?? thanks

could you suggest something according to my simulation plotting?? thanks

Click to expand...

(1) All the four terms should be considered. Besides, Rg and Rl should be minimized through careful layout.

(2) I'm sorry i made a lot of mistake in the paragraph. It's my fault due to headache .

I mean, those model engineer who did not model the induced gate noise can "get a MORE ACCURATE noise performance" by their modified BSIM3 model.

About 4 years ago, when the mainstream process is still 0.35um CMOS, somebody even uses 0.5um CMOS to design RFIC. Under those parameters, the ωT is smaller to the device nowaday, so the complicated term dominates (because it is in proportional to (ω0/ωT)) . As the line width scales down and the ωT gets higher, the complicated term becomes smaller. And because the resistance of poly arises due to slimmer line width, the (Rg/Rs) and (Rl/Rs) arises. With bad layout and innocent design at input device, the NF can't be lowered down even you know the optimum point.

(3) The graph is correct.

i see. as the ling length scaling down, the ωt is increasing, so the NFmin is decreasing. however, the Rg is increasing ,so the term Rg/Rs is bigger. but it can be minimized through correct layout design. that's all??
thanks!!

could you recommend some books or papers about RFIC layout design?

Yes.

There seems no book is talking about RFIC layout, but some IEEE papers describe their chip layout in the content.

But for general ananlog layout, you can refer to the book--- "The Art of Analog Layout", it's a great book.