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setup and hold time violations

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vivek

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Hi
Please clarify this :

If i have to choose between two circuits, one with setup time violation and other with hold time violation, which should be my choice?

What are ways of fixing setup and hold time violations in rtl code?
Thanks in advance
 

setup means delay is longer than one cycle,you can
reduce combination logic between two ffs,hold violation can let synthesis tool fix
 

If I must do the choice, I will do the latter , because the latter can be fixed by adding some combinational logics so easily
 

I think you should choose the circuit with hold time violations.

because for hold time violation, you can add delay to fix it,

but for setuo time, you only can redesign your circuit to improve

speed.

best regards



vivek said:
Hi
Please clarify this :

If i have to choose between two circuits, one with setup time violation and other with hold time violation, which should be my choice?

What are ways of fixing setup and hold time violations in rtl code?
Thanks in advance
Click to expand...
 

    V

    vivek

    Points: 2
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setup violation can be resolved by running system at a lower clock if possible... hold time violation can be reduced by adding buffers between FF's on data path.
 

Circuit with hold time violation, u can fix it during layout (P&R) or in DC. Adding delays (buffers)

If u have the luxury to redesign or optimize the circuit...then go ahead with setup violation circuit dude.


Finally, it is ur call. I only give my opinion.

Hope it helps :)
 

    V

    vivek

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Circuit with setup violations is bound to fail unless the operating frequency is reduced.

Fixing hold violations is easier and doesnt effect ckt speeds that much so picking up that design is batter as it can be corrected easily.
 

hi vivek,
There is no question of choice between the two. Bith can be corrected. The setup violation can be corrected by running your design at lower frequency or yes redesign your logic so that it gives better performance than the original one.
Hold violation is not dependent on the freq. of operation. That can be eliminated by lenghtning the trace in P&R or by adding buffers in the data path so that the data arrives a little late with respect to the active clock edge.
 

Hi, this discussion has been done earlier and concluded like this:


As, set-up violations can be corrected even after design is implemented/prototyped, by running it at a reduced clock frequency; Hold-time violations need buffers to be added in the critical path (data) & so cannot be rectified after implementation. So, Hold-time violation is an obvious choice. what do the teachers say?
 

select the latter with hold violation ! hold violation will be fixed in the back-end!
 

I think selecting set-up violation is better.bcoz as told earlier set-up can be fixed by reducing the operting frequence.if we are unable to fix the hold problem ,we cannot proceed further
 

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