Principal of Pipelined ADC

Hi guyz,

I am trying to understand the principal operation of Pipelined ADC. The architecture is attached. From this acrhitecture, within each stage the analog input is first sampled and held. Then it is coarsely quantized by a sub-ADC to resolve 2 bits. Then the output from sub-ADC will be converted back to analog value by using DAC and this output will be subtracted from the original input. This quantization error is then restored to the original full-scale range by an amplifier with gain 2.

I need to know in details why is this happening and how does the residues can represent the original analog input voltage?

Why we choose amplifier with gain 2?

When we say the quantization error is restored to the original full-scale range by gain of 2, what does it actually mean? (I'm confused!!)

I appreciate any comments.

Thanks in advance

1st stage: compare input 0.7V with 0.5V(mid) and 0.7>0.5 ==> bit '1' and residue =0.7-0.5=0.2 then amplify residue 0.2*2=0.4V

2nd stage: compare the amplified residue 0.4V with 0.5V and 0.4<0.5 ==> bit '0' and residue=0.4-0=0.4 then amplify residue 0.4*2=0.8

3rd stage: compare the amplified residue 0.8V with 0.5V and 0.8>0.5 ==> bit '1' and residue=0.8-0.5=0.3 then amplify residue 0.3*2=0.6

4th stage: compare the amplified residue 0.6V with 0.5V and 0.6>0.5 ==> bit '1' and residue=0.6-0.5=0.1 then amplify residue 0.1*2=0.2

5th stage:.....
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Nth stage: resolve the LSB

baker's book is very good reference if you want to understand pipelined ADC.

What is the full title of the book? Do you know where I can find the e-book version? Is it available in the forum?

many thanks
-snoop835-

CMOS Circuit Design, Layout, and Simulation
R. Jacob Baker, Harry W. Li, David E. Boyce

Read mixsignal section. I also struggled to understand pipelined ADC. But after read this book, I really understand the architecture. Other books and paper only give rough idea.