Class D Power Amplifier...

In a class D amplifier, The Lee book says that since the 2 transistors are acting like switches (see the attached figure below) the primary of transformer T2 has its ends alternatively got to ground. and the other ends alternatively got to 2Vdd by transformer action.
I didn't understand why does the other end go to 2*Vdd when one end goes to ground???

The output transformer has centre-tap and because of this the top winding delivers to the output Vdd whereas the bottom part -Vdd.
So the output peak-to peak voltage is 2Vdd.
Regards,
IanP

The waveforms for a single transistor given in the book are attached below. I understand that the top half winding gives Vdd in 1 cycle and the bottom winding gives Vdd in the next cycle in the other direction. But what I don't understand is when either of the transistor is how does the transformer force its drain to go to 2Vdd, as the waveform shows?

It doesn't happen in two cycles. It happens in one cycle.
If the output were floating you would have +Vdd in the first half cycle (top part of the transformer primary) and -Vdd in the 2nd half of the same cycle (bottom winding of the transformer primary). As a result you have output signal at th same frequency as the control signal, but the output referenced to GND is 2*Vdd.
Regards,
IanP

I am sorry but I still do not understand. Let me describe the whole picture as I see it.

vdrive is suppose a sinusoidal of frequency wo, so the primary of T1 has a voltage vdrive in 1 direction (topside positive) during Π/wo (Half period) and the other direction(bottomside positive) during the other half of the input period. So now this variation on the secondary gets transferred as follows.
During the 1st half of the period M2 is ON therefore assuming ideal switching action the drain and thus the topside of primary winding of T2 is at 0 volt. The mid winding of T2 is at VDD. Also during this half period M1 is OFF therefore its drain is floating, so I don't understand why its potential is 2Vdd, I was thinking it will be just Vdd.
Now in the next half of the cycle M2 is OFF and its drain is floating, and M1 is ON and its drain thus the bottomside of primary of T2 is ground. So now why does the floating drain og M2 have to be at 2Vdd? Shouldn't it be just Vdd?
Sorry for being stuck.

you can simulate the circuit using OrCad.
but the complete solution for power amplifier in class D is here:
h**p://www.geocities.com/CapeCanaveral/9096/index.htm

Do you know what a transformer is???
If you know you would understand that on the part that is connected the cut-off transistor there will be a Vdd inducted ACROSS the winding, it will add to the Vdd of the center tap to get 2Vdd on the cut-off transistor.

Oops sorry ya I guess I was thinking too hard !