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Multiple varying delays to signals in VHDL

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arifboy

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Missing CODE or SYNTAX tags [ Added by moderator ]
I am working on a VHDL code to insert multiple varying delays to signals. I have shown code below and expected waveforms and present waveforms respectively too. How can the code be changed to get desired waveforms?


Code VHDL - [expand]
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int := conv_integer(pc);
   
    wait until rising_edge(clk);
 
        if (int >= 0 and int <= 500) then  -- alu/j
            load_logic <= '0';
            store_logic <= '0';
            branch_logic <= '0';
            wait for 20 ns; alu_logic <= '1';    
            wait for 20 ns; alu_logic <= '0';
      
    
        elsif (int >= 504 and int <= 600) then --load
            alu_logic <= '0';
            store_logic <= '0';
            branch_logic <= '0';
            wait for 40 ns; load_logic <= '1';   
            wait for 20 ns; load_logic <= '0';
 
        elsif (int >= 604 and int <= 700) then -- store
            alu_logic <= '0';
            load_logic <= '0';
            branch_logic <= '0';
            wait for 60 ns; store_logic <= '1';
            wait for 20 ns; store_logic <= '0';   
 
        else --- br/j  
            alu_logic <= '0';
            load_logic <= '0';
            store_logic <= '0';
            wait for 80 ns; branch_logic <= '1';
            wait for 20 ns; branch_logic <= '0';        
 
        end if;


right.png
wrong.png
 
Last edited by a moderator:
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What are you trying to achieve? If you are targeting to synthesizable HDL, timed wait statements must replaced by clocked timers. 10 ns resolution (100 MHz clock) should be no problem with recent FPGA or CPLD.
 
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FvM said:
What are you trying to achieve? If you are targeting to synthesizable HDL, timed wait statements must replaced by clocked timers. 10 ns resolution (100 MHz clock) should be no problem with recent FPGA or CPLD.
Click to expand...
In Simulations, the waveforms which I target must be possible, but I failed to get using both 'wait' and 'after' and even with combo of these two too. So maybe I am missing some key points. Synthesis can be achieved by a different approach, but first thing is Simulations and get the required behavior
 
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Combination of wait_until rising_edge(clk) and wait for is most likely not achieving what you want.
I see two problems why the expected waveform (upper picture) isn't achieved:

1. wait for is blocking the whole process. Alternative cases aren't evaluated before the last active wait for has timed out.
2. your code has no means to generate a specific signal only once, it's not corresponding to expected waveform.

I would choose a different approach, delay generated by counting clock cycles. Having spearate timers for each signal, they can be generated independant of other timers. The code will be also synthesizable.
 
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arifboy said:
wait until rising_edge(clk);
Click to expand...
Shows that this is a testbench use case!

You can use "wait" statements to wait for a specific amount of time.
To delay a signal before assigning it to some other signal at the testbench, you can use transport dealy modeling (e.g. sig2 <= sig1 after 7 ns).

But since it seems you are writing a test bench for some sequential logic (cpu, etc...). So I would highly advise you to write a testbench containing process statements which has the clock in the sensitivity list. You will have a lot of control and clear understanding of what is being done. I do not support the way you have written the TB to simulate your DUT.

Additionally - the advice given in the post above!
 
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dpaul said:
Shows that this is a testbench use case!

You can use "wait" statements to wait for a specific amount of time.
To delay a signal before assigning it to some other signal at the testbench, you can use transport dealy modeling (e.g. sig2 <= sig1 after 7 ns).

But since it seems you are writing a test bench for some sequential logic (cpu, etc...). So I would highly advise you to write a testbench containing process statements which has the clock in the sensitivity list. You will have a lot of control and clear understanding of what is being done. I do not support the way you have written the TB to simulate your DUT.

Additionally - the advice given in the post above!
Click to expand...
This is program code, not the testbench. I was using after previously as you mentioned but second after nullifies first one for each of if else above. Wait actually is doing something at least, but output is not right one. I think its not possible to simulate it in this way in VHDL, at least by using the transport, after and wait given in language itself.
 
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arifboy said:
This is program code, not the testbench
Click to expand...
Then just put this in the garbage bin (yes I am being this straightforward) and write fresh RTL code in which you have process blocks with sensitivity lists.
You must write synthesizable RTL code and there are rules to write synthesizable RTL code.
--- Updated ---

arifboy said:
Synthesis can be achieved by a different approach, but first thing is Simulations and get the required behavior
Click to expand...
This approach for logic design is also completely wrong!

You must FIRST write RTL code which is synthesizable and then write code for test bench, which will generate peripheral signals to verify your synthesizable code using behavorial simulation.

Nevertheless follow a good tutorial for RTL design and learn the basics first!
 
Last edited:
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You need need the execution to happen only once during the frame. Declare checker and try this:

if (int >= 0 and int <= 500) then -- alu/j
checker <= '0'
load_logic <= '0';
store_logic <= '0';
branch_logic <= '0';
If checker = '0' then
wait for 20 ns; alu_logic <= '1';
wait for 20 ns; alu_logic <= '0'; checker <= '1';
end if;

Add checker to all cases in this way.

Here you're just using checker to get it to happen just once. If this doesn't solve it, then we will modify it to get it to work.
 
Last edited:
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Akanimo said:
You need need the execution to happen only once during the frame. Declare checker and try this:

if (int >= 0 and int <= 500) then -- alu/j
checker <= '0'
load_logic <= '0';
store_logic <= '0';
branch_logic <= '0';
If checker = '0' then
wait for 20 ns; alu_logic <= '1';
wait for 20 ns; alu_logic <= '0'; checker <= '1';
end if;

Add checker to all cases in this way.

Here you're just using checker to get it to happen just once. If this doesn't solve it, then we will modify it to get it to work.
Click to expand...
With your suggestion the waveform came closer to what the expected waveform is, but still not exactly there. I have attached a photo of that. You suggested if, I used while too with other lines exactly as you mentioned, but that didn't work too according to expectation.
 

Attachments

  • modified.png
    modified.png
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Akanimo said:
Let's see your latest code then, and we can take a further look at it.
Click to expand...
Its the same, I just added those lines of you with signal checker..Intiially there is extra cycle added as you see in waveform. It is taking an extra cycle instead of just one, to make Alu_logic a 1. You cant simulate it at your end?
--- Updated ---

dpaul said:
Then just put this in the garbage bin (yes I am being this straightforward) and write fresh RTL code in which you have process blocks with sensitivity lists.
You must write synthesizable RTL code and there are rules to write synthesizable RTL code.
--- Updated ---


This approach for logic design is also completely wrong!

You must FIRST write RTL code which is synthesizable and then write code for test bench, which will generate peripheral signals to verify your synthesizable code using behavorial simulation.

Nevertheless follow a good tutorial for RTL design and learn the basics first!
Click to expand...
You yourself dont know VHDL, thats why you suggested use of after statement. After statement gives inertial delay, but you think its transport delay. I have already told you after statement doesn't work for this program. You are just wasting time of both of us. Why dont you learn VHDL first, before telling me to learn it??
 
Last edited:
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arifboy said:
You yourself dont know VHDL, thats why you suggested use of after statement. After statement gives inertial delay, but you think its transport delay. I have already told you after statement doesn't work for this program. You are just wasting time of both of us. Why dont you learn VHDL first, before telling me to learn it??
Click to expand...
That was because when I saw statements like "wait until rising_edge(clk);" in your post, I thought you were writing testbench code. So I wanted to tell you about various delays that can be used in VHDL testbench code. But at Post #6 you told me that it was synthesizable code!
--- Updated ---


Also pay attention to Post #2 by @FvM.

:LOL:....my bread and butter depends on the quality of VHDL code I write and a newbie is telling me to learn VHDL, OMG!
Sorry that I tried to help an arrogant Newbie. I am definitely out of this thread!
 
Last edited:
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dpaul said:
lol....you newbies are so modest!
Sorry that I tried to help you. I am out of this thread.
Click to expand...
Dont waste my time anymore, my focus is towards my code and algorithms which can be implemented on it, not towards people like you

dpaul said:
That was because when I saw statements like "wait until rising_edge(clk);" in your post, I thought you were writing testbench code. So I wanted to tell you about various delays that can be used in VHDL testbench code. But at Post #6 you told me that it was synthesizable code!
--- Updated ---


Also pay attention to Post #2 by @FvM.

:LOL:....my bread and butter depends on the quality of VHDL code I write and a newbie is telling me to learn VHDL, OMG!
Sorry that I tried to help an arrogant Newbie. I am definitely out of this thread!
Click to expand...
I never told you my code is synthesizable code, your bread and butter doesn't, but seems like your drinking is depending on it. Thinking with drinking wow, you must be hanging too much in a fantasy world of thinking. Read comments carefully, without drinking lol
--- Updated ---

Akanimo said:
Let's see your latest code then, and we can take a further look at it.
Click to expand...
Any other suggestions you have? Were you able to see the result of if block addition at your end?
 
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Code: 
if (int >= 0 and int <= 500) then -- alu/j
load_logic <= '0';
store_logic <= '0';
branch_logic <= '0';
wait for 20 ns; alu_logic <= '1';
wait for 20 ns; alu_logic <= '0'; checker <= '1';
wait on int; -- new modification

Try this. Comment out all the checker lines. And please, let's not deviate from the goal of getting and giving help to making abusive comments. Add the statement 'wait on int' to all if conditions.

If this doesn't solve it, then I'll have to run the simulator myself if you will post all of code here.
--- Updated ---

Let the additional line be the last line in each of the if conditions.
 
Last edited:
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There are apparently misunderstandings what "program code" means. I would also read it as synthesizable VHDL, anyway.

I think the biting discussion tone has been brought up by original poster's big talk which doesn't sound inviting to me. Therefore only a scarse comment. I believe the problem can be well solved by writing solely synthesizable VHDL, this way you don't need to care if it's for simulation or hardware.
 
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Akanimo said:
Code: 
if (int >= 0 and int <= 500) then -- alu/j
load_logic <= '0';
store_logic <= '0';
branch_logic <= '0';
wait for 20 ns; alu_logic <= '1';
wait for 20 ns; alu_logic <= '0'; checker <= '1';
wait on int; -- new modification

Try this. Comment out all the checker lines. And please, let's not deviate from the goal of getting and giving help to making abusive comments. Add the statement 'wait on int' to all if conditions.

If this doesn't solve it, then I'll have to run the simulator myself if you will post all of code here.
--- Updated ---

Let the additional line be the last line in each of the if conditions.
Click to expand...
'wait on pc' works, not 'wait on int', but your idea was right, once I saw it I realized it would work and that was what happened. I kept trying wait until on this code, instead of giving wait on a chance too. I would not have even cared if he commented rudely on my discussion with him. I thought his comment on my discussion with you, could distract you. Thanks
 
Upvote 0 Downvote
Akanimo said:
Code: 
if (int >= 0 and int <= 500) then -- alu/j
load_logic <= '0';
store_logic <= '0';
branch_logic <= '0';
wait for 20 ns; alu_logic <= '1';
wait for 20 ns; alu_logic <= '0'; checker <= '1';
wait on int; -- new modification

Try this. Comment out all the checker lines. And please, let's not deviate from the goal of getting and giving help to making abusive comments. Add the statement 'wait on int' to all if conditions.

If this doesn't solve it, then I'll have to run the simulator myself if you will post all of code here.
--- Updated ---

Let the additional line be the last line in each of the if conditions.
Click to expand...
Is there a way to remove the extra cycle each signal is taking after the first output? Seems like Alu_logic output is taking extra cycle, and Load logic and its delay then starts and takes effect. The same way Load_logic is going into region of store_logic, it all continues to branch logic too. 40ns is actually giving delay of 60ns thus, 60ns giving delay of 80ns. Why this extra 20ns each time?
 
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