Feantar
Newbie
Hello,
I am working with GTY4E_channel and GTY4E_common Xilinx's IP primitives with VHDL via fiber connectors on 2 pcb boards (let's call these boards "ATK" and "SAB"). I am providing communication at 8 Gbps speed over a single lane. I am providing the reference clocks of these boards (MGT_REF_CLK) from an integrated called AD9528. I connected the output of an oscillator that produces 40 mhz to the VCXO input of AD9528 on "ATK" board. In this way, I will not use PLL1 and will only produce the signals with PLL 2. From here, I am producing both a reference clock for GTY and an external clock for "SAB" board (200 mhz reference clock for GTY, 40 Mhz reference clock for "SAB" entering REFA of AD9528). I give this reference clock from MMCX connector and get it from "SAB" side with SMA. I get AD9528 REFA of "SAB" board from "ATK" as External and from here I generate reference clock (200mhz) for GTY_ref_clk in "ATK" board. When I connected them with fiber cable and did their tests, I saw that they did not work. Incoming data comes differently. First, the data I transmit are Special K Characters 28K5(BC) and 28K0(1C). I transmit them until I find 256 in order. First, it needs to find 28k5 256 times, then it needs to wait for 28k0 256 times and then they should enter the link. However, when I look at it with the Chip scope, I see that the incoming data (rx_data_o at the output of GTY) is different. For example, the data which I expected to be BC comes as F7. I decreased the speeds, et pre_cursor and post_cursor to improve signal integrity, changed the polarity etc. none of them worked. The CDRLOCK signal is always 1.
Does anyone have a suggestion on what to do?
I am working with GTY4E_channel and GTY4E_common Xilinx's IP primitives with VHDL via fiber connectors on 2 pcb boards (let's call these boards "ATK" and "SAB"). I am providing communication at 8 Gbps speed over a single lane. I am providing the reference clocks of these boards (MGT_REF_CLK) from an integrated called AD9528. I connected the output of an oscillator that produces 40 mhz to the VCXO input of AD9528 on "ATK" board. In this way, I will not use PLL1 and will only produce the signals with PLL 2. From here, I am producing both a reference clock for GTY and an external clock for "SAB" board (200 mhz reference clock for GTY, 40 Mhz reference clock for "SAB" entering REFA of AD9528). I give this reference clock from MMCX connector and get it from "SAB" side with SMA. I get AD9528 REFA of "SAB" board from "ATK" as External and from here I generate reference clock (200mhz) for GTY_ref_clk in "ATK" board. When I connected them with fiber cable and did their tests, I saw that they did not work. Incoming data comes differently. First, the data I transmit are Special K Characters 28K5(BC) and 28K0(1C). I transmit them until I find 256 in order. First, it needs to find 28k5 256 times, then it needs to wait for 28k0 256 times and then they should enter the link. However, when I look at it with the Chip scope, I see that the incoming data (rx_data_o at the output of GTY) is different. For example, the data which I expected to be BC comes as F7. I decreased the speeds, et pre_cursor and post_cursor to improve signal integrity, changed the polarity etc. none of them worked. The CDRLOCK signal is always 1.
Does anyone have a suggestion on what to do?
