What is the Big advantage of parasitic inductance in RF Trace?

You forgot to tell the application. It looks like RF transmitter or similar, so the matching network is optimized for a specific transfer function, including filtering of harmonics. I guess you don't want to redesign the matching network, most likely you don't even have all information required to do so.

Reading the layout application note strictly, it is just telling you that the short trace is intentional and must not be removed during layout implementation. It does not ask to add higher series inductance here, this would most likely kill the designed matching.

I guess, a 0201 chip inductor won't save space in this place if you consider room for pads and minimal component-to-component clearance.

If you want to save space by changing the layout, then you should be prepared to completely redesign and verify the matching network from scratch. If you don't have the time and equipment to do that, then I strongly suggest you leave it alone.

Also keep in mind the PCB stackup will also affect this network.

The sentence should be written without word "parasitic", as: "The additional inductance of this short trace is part of the matching network".
The inductance of a microstrip line is a fact, not a parasitic, and its value is part of the line impedance equation Zo=SQRT(L/C).
The LC equivalent of a microstrip transmission line is a low pass filter. To get the same characteristic using lumped components, you need a series inductor and at least one shunt capacitor, maybe two.

I understand that ;
The parasitic inductance (ESL) of a trace is proportional to the log of gap to the return path either coplanar pwr/ground or sub-layer plane gap.
The inductance reduces inversely with the log of width of the trace. Thus a chip <1nH will reduce in value a 0201 chip minimum is 0.4 nH.
The parasitic capacitance and ESL are proportional to length but for thin traces a thin dielectric to coplanar gnd traces are needed to get 50 Ohms otherwise the Zo is much higher (150).

For a w/h ratio =0.1 ESL is about 0.8 nH/mm and can vary +/50% with large variations in w/h as well as pF/cm

You should have asked a better prompt to Grok3


ESL=? w=0.15 mm over gnd plane h= 1.5

------------------------------------------------------ Grok3
It looks like you’ve refined your question about the equivalent series inductance (ESL) of a trace, specifying a width (w) of 0.15 mm over a ground plane with a height (h) of 1.5—likely meaning the substrate thickness (h) between the trace and ground plane is 1.5 mm. This differs from your previous question (0.15 inches wide over a 1.5-inch ground plane), so I’ll assume this is a new scenario with metric units and calculate the ESL accordingly. Let’s proceed with a microstrip inductance estimation, clarifying assumptions as needed.
Setup and Assumptions

• Trace Width (w): 0.15 mm (150 μm).
• Substrate Thickness (h): 1.5 mm (distance from trace to ground plane).
• Ground Plane: Assumed wide enough to act as an infinite plane (e.g., >5× trace width, or >0.75 mm wide), since you didn’t specify its dimensions.
• Trace Length (L): Unspecified, so I’ll compute inductance per unit length (nH/mm) and let you scale it.
• Material: FR-4 dielectric, ε_r ≈ 4.5 (common PCB material).
• Trace Thickness (t): ~35 μm (1 oz copper, standard), though it has minimal impact on ESL here.

This describes a microstrip: a narrow trace over a dielectric above a ground plane. The ESL depends on the geometry (w, h, L) and dielectric properties.
Microstrip Inductance Calculation
The inductance per unit length (L’) of a microstrip can be derived from its characteristic impedance (Z₀) and phase velocity (v_p):
L′=Z0vp
Step 1: Effective Dielectric Constant (ε_eff)
εeff=εr+12+εr−12⋅11+12⋅hw

• εr=4.5
• h=1.5 mm
• w=0.15 mm
• h/w=1.5/0.15=10

εeff=4.5+12+4.5−12⋅11+12⋅10
=2.75+1.75⋅11+120
=2.75+1.75⋅1121
=2.75+1.75⋅111≈2.75+0.159≈2.91
Step 2: Characteristic Impedance (Z₀)
For a microstrip (w/h < 1):
Z0=120πεeff⋅(wh+1.393+0.667⋅ln⁡(wh+1.444))
Alternatively, for w/h << 1 (here, w/h = 0.1), a simpler wide-plane approximation works:
Z0≈60εeff⋅ln⁡(8hw+w4h)

• w/h=0.1
• 8h/w=8⋅10=80
• w/4h=0.1/4=0.025
• 8hw+w4h=80+0.025=80.025
• ln⁡(80.025)≈4.382

Z0=602.91⋅4.382
=601.706⋅4.382≈35.17⋅4.382≈154 Ω
Step 3: Phase Velocity (v_p)
vp=cεeff=3×1082.91≈3×1081.706≈1.76×108 m/s
Step 4: Inductance per Unit Length (L’)
L′=Z0vp=1541.76×108≈8.75×10−7 H/m=875 nH/m
Convert to mm (1 m = 1000 mm):
L′=875/1000=0.875 nH/mm
Step 5: Total ESL

• ESL = 0.875 nH per mm of trace length.
• Example: For a 10 mm trace, ESL = 0.875 × 10 = 8.75 nH.

Validation

• For a narrow trace (w/h = 0.1), inductance is higher due to less field confinement, and 0.875 nH/mm (875 nH/m) is reasonable. Typical microstrip values range from 0.2–1 nH/mm, depending on w/h.
• Previous calc (w = 0.15 in, h = 0.062 in) gave 6.76 nH/in (0.266 nH/mm), but here w/h is much smaller (0.1 vs. 2.42), increasing Z₀ and thus L’.

Adjustments

• Ground Plane Size: If “h=1.5” meant a 1.5 mm-wide plane (not height), we’d need a coplanar waveguide model, but I assumed h as substrate thickness (standard microstrip convention).
• Length: Scale by your trace length.
• Dielectric: If not FR-4 (e.g., air, ε_r = 1), ESL would rise slightly (e.g., ~1 nH/mm).

Final Answer
For a 0.15 mm wide trace, 1.5 mm above a ground plane:

• ESL ≈ 0.875 nH/mm of length.
• Example: 100 mm trace → 87.5 nH.

-------

looks right
don't modify a design with verified results unless you know the consequences. The trace ESL is small but higher Q and more consistent than a lumped 201 part. Don't change if < 1nH unless you have simulated the 3D conductor geometry with all parameters including Rs, Csh, Zo, s21, s11, f

Your question is missing too many assumptions to analyze completely.

- Spectral pass and stop bands, designed CLC parts and expected ESL of 1st path.
- impedance transformation values ?
- dielectric type , nearest gap to signal ground, dimensions?
- All 0201 parts are not the same I max, Q and SRF, with possible conflicts with AQL list
- tolerances to design specs?
- cost / benefits of alternative, Is it significant?

you could have told us it was Fig 2.3 https://www.silabs.com/documents/pu...an928.2-efr32-series2-layout-design-guide.pdf

This is a rough approximation where I assumed 800 pH.



I assumed a driver resistance.
It seems SI's design is good depends greatly on attenuation and power level of harmonics.

Zebra123 said:

In addition, even though we have simulation tool, it is difficult for us to decide the actual value of the parasitic inductance precisely.

Click to expand...

This is measured vs. simulated for a 432 MHz filter where I implemented the shunt inductor in layout, instead of using SMD inductors.



Using the layout is very clearly defined. Using SMD requires a very good S-parameter model of the actual SMD response including parasitics. The xx nH SMD has a strong variation of inductance over frequency, due to parasitics like capacitance betweem the turns. You need really good RF component models for design success.

Complete story:

Very nice detail from Dr. Muelhaus highlights the importance of trimming a critical notch by removing more capacitance from the voided ground plane while very slightly increasing the inductance to tune the notch. Although his excellent example is a CLC HPF with a notch at 1/3rd of BW unlike the question of a LCL LPF, without a notch at 3f, that can be done when higher powers demand it.

Conclusions:

A stripline inductor is far more accurate than a discrete part where you have removed the return path ground, when it is critical.
Tiny discrete LC parts have poor tolerances due to differences in PCB gaps to the nearest signal ground.
You may still need a knife in the above prototype and may prefer to have a notch if you raise your Tx power to get a -50 dB harmonic suppression.

A chip inductor doesn't have same behaviour as a transmission line. Otherwise we could inductors instead of transmission line.
The operating frequency is low ( sub-GHz) this length does not change much. If the performance is not achieved well, a fine tuning might be necessary.

BigBoss said:

A chip inductor doesn't have same behaviour as a transmission line. Otherwise we could inductors instead of transmission line.
The operating frequency is low ( sub-GHz) this length does not change much. If the performance is not achieved well, a fine tuning might be necessary.

Click to expand...

Yes of course, T-lines have an ideal constant Zo, while discrete L's have less distributed capacitance even if added under the part and also much lower Q's. (Thus rising Z and higher DCR) (Although this was a low Q filter).

In this case if space was not a premium one may choose all L's with microstrip with gnds , although ε_r lowers with rising f and has an ε_eff that is the rms mean of {air=1 on the topside with ε_r on the bottom} it often causes initial design errors from a learning curve. The proximity to signal gnd return is a key omission{ thickness of ε_r for stripline or high-Z line with a gnd keep-out under the stub, as in @volker's example.

Conclusion: Ground layer was never included in the question has a significant result in both discrete and microstrip nH choices. Propagation delays of the first L trace achieve the required 0.8 nH perhaps better than a discrete part for accuracy. The next LC parts could also have been microstrip, (2.3 nH, 1.1 nH) but space was conserved with adequate < 20mW performance.

Pardon me if I have confused the reader with high-Z line filters and microstrip filters. The key is in the ground plane impedance.
Unlike Volker's ungrounded stub inductor to trap image at f/3, you want a Tx's passband filter inductor's EM filed confined beneath the trace to a ground return to reduce radiation losses.

BigBoss said:

A chip inductor doesn't have same behaviour as a transmission line.

Click to expand...

Transmission lines are characterized by their line impedance Z = sqrt(L'/C')

If you look at the layout screenshot, that line has no ground below, so it behaves mostly inductive, with very little shunt C. It is valid to treat this like an inductor, and ignore the effect of the really small shunt C.

volker@muehlhaus said:

Transmission lines are characterized by their line impedance Z = sqrt(L'/C')

If you look at the layout screenshot, that line has no ground below, so it behaves mostly inductive, with very little shunt C. It is valid to treat this like an inductor, and ignore the effect of the really small shunt C.

Click to expand...

That's what I called a high-Z line inductor with a fairly remote ground. The leakage there was just a trap from Rx interference at 144 MHz for EMI is not an issue, but 3rd harmonic of said nearby Tx might steam up the glasses on that Ham's passband.

The lesson for @Zebra123 is not to be afraid to ask better questions and make misteaks often then correct them quicker. (like Elon)

A more interesting filter design is SI's higher order strategy starting on p17 of 42 https://www.silabs.com/documents/public/application-notes/an930.2-efr32-series-2.pdf which again increases in complexity with output power of harmonics with fundamental at 0, 10 , 20 dBm.