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calculate approximately maximum clock frequency with TNS.

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I have a signal with a Worst Negative Slack (WNS) of 0.13ns after synthesis on an FPGA with a clock running at 1Ghz. I want to determine the maximum clock frequency that can accommodate this 30ns WNS. Given that the WNS is quite large,
So, I can calculate the new maximum frequency as 1000/1.13 = 884.5Mhz

But I want to know if I get TNS(281.48) information from synthesis, is it helpful or affect to calculation of maximum effective clock frequency?
If there is a meaning, how do I calculate approximately maximum effective clock frequency with TNS information only?
 
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TNS is not helpful because it can come from 1 path, 2 paths, 300 paths. WNS itself is not the most helpful either, you would have to iterate with a couple synthesis runs to approximate the highest frequency of operation.
 
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On FPGA，routing will take about 50%~75% cycle time. And usually the timing from synthesis in inaccurate, you'd better run P&R and get timing report after it.
Then you can use your method to estimate the approximate maximal freq.

For ASIC, timing report from synthesis is more accurate than that of FPGA.
 
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