coshy
Member level 5

I have a signal with a Worst Negative Slack (WNS) of 0.13ns after synthesis on an FPGA with a clock running at 1Ghz. I want to determine the maximum clock frequency that can accommodate this 30ns WNS. Given that the WNS is quite large,
So, I can calculate the new maximum frequency as 1000/1.13 = 884.5Mhz
But I want to know if I get TNS(281.48) information from synthesis, is it helpful or affect to calculation of maximum effective clock frequency?
If there is a meaning, how do I calculate approximately maximum effective clock frequency with TNS information only?
So, I can calculate the new maximum frequency as 1000/1.13 = 884.5Mhz
But I want to know if I get TNS(281.48) information from synthesis, is it helpful or affect to calculation of maximum effective clock frequency?
If there is a meaning, how do I calculate approximately maximum effective clock frequency with TNS information only?